公开(公告)号：US20220093402A1

公开(公告)日：2022-03-24

申请号：US17029023

申请日：2020-09-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU ,  Rou-Wei WANG

IPC: H01L21/28 ,  H01L21/033 ,  H01L29/40

Abstract: A method of manufacturing a semiconductor device is provided. A precursor structure is formed, in which the precursor structure includes a patterned substrate having at least one trench therein, an oxide layer covering the patterned substrate, and a nitride layer on the oxide layer and exposing a portion of the oxide layer in the trench. A first barrier layer and a first gate structure is formed on the oxide layer. A portion of the first barrier layer is removed with an etchant including CF4, C2F6, C3F8, C4F8, F2, NF3, SF6, CHF3, HF, COF2, ClF3 or H2O2 to expose a sidewall of the oxide layer. A second barrier layer is formed on the first gate structure and the oxide layer. A portion of the second barrier layer is removed with the etchant. A second gate structure is formed on the second barrier layer.

公开(公告)号：US20220069070A1

公开(公告)日：2022-03-03

申请号：US17010843

申请日：2020-09-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H01L49/02

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternatively stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

公开(公告)号：US20220351961A1

公开(公告)日：2022-11-03

申请号：US17243159

申请日：2021-04-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Rou-Wei WANG ,  Jen-I LAI ,  Chun-Heng WU ,  Jr-Chiuan WANG ,  Chia-Che CHIANG

IPC: H01L21/02 ,  H01L21/762

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

公开(公告)号：US20220020752A1

公开(公告)日：2022-01-20

申请号：US16933976

申请日：2020-07-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H01L27/108 ,  H01L21/311

Abstract: A method for manufacturing a capacitor includes: providing a substrate and a multilayer structure; forming a recess in the multilayer structure; forming a first electrode layer on a surface of the recess; performing a selective etching treatment to remove the first and second stack material layers; performing a selective vapor phase etching treatment to the first electrode layer to form a smaller thickness of the first electrode layer; and forming a dielectric layer and a second electrode layer in which the dielectric layer is between the first and second electrode layer.

公开(公告)号：US20240357798A1

公开(公告)日：2024-10-24

申请号：US18305375

申请日：2023-04-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Heng WU

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: The semiconductor structure includes a substrate, a plurality of bitline structures on the substrate, a spacer structure on side walls of each of the plurality of bitline structures, a plurality of conductive structures on the substrate, and a dielectric layer between the plurality of bitline structures and the plurality of conductive structures. The spacer structure includes an inner sub-spacer, an outer sub-spacer, and an air gap between the inner sub-spacer and the outer sub-spacer. Each of the plurality of conductive structures is separated from the other by the plurality of bitline structures. A first portion of the dielectric layer in direct contact with the plurality of bitline structures has a first maximum height, a second portion of the dielectric layer in direct contact with the plurality of conductive structures has a second maximum height, and the first maximum height is larger than the second maximum height.

公开(公告)号：US20240049439A1

公开(公告)日：2024-02-08

申请号：US17818007

申请日：2022-08-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chia Che CHIANG ,  Jen-I LAI ,  Chun-Heng WU

IPC: H01L27/108

CPC classification number: H01L27/10852

Abstract: A method of forming semiconductor structure includes forming a dielectric stack over a substrate. A mask layer is formed over the dielectric stack. A first opening is formed in the mask layer to expose dielectric stack. A second opening is formed in the dielectric stack to expose the substrate, wherein the second opening is communicated with the first opening. A fill layer is formed in the first opening and the second opening. The mask layer and the fill layer are removed such that sidewalls of the dielectric stack are exposed. A capacitor is formed in the second opening of the dielectric stack.

公开(公告)号：US20220102347A1

公开(公告)日：2022-03-31

申请号：US17643411

申请日：2021-12-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/92

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

公开(公告)号：US20250151256A1

公开(公告)日：2025-05-08

申请号：US18504426

申请日：2023-11-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Heng WU

IPC: H10B12/00 ,  H01L21/768

Abstract: A method includes a number of operations. An oxide layer is formed in an isolation trench over a substrate. A liner is formed over the oxide layer. The liner is oxidized. An implant region is formed over the substrate after the liner is oxidized. The oxide layer and the liner are etched after the implant region is formed. A word line structure is formed over the substrate and across the oxide layer and the liner.

公开(公告)号：US20240268099A1

公开(公告)日：2024-08-08

申请号：US18164634

申请日：2023-02-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Heng WU

IPC: H10B12/00 ,  H01L21/311 ,  H01L21/762

CPC classification number: H10B12/482 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762

Abstract: A semiconductor structure includes a semiconductor substrate, an isolation structure, and a conductive structure. The isolation structure is located on the semiconductor substrate. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface. The conductive structure has a trench. The trench extends to the second top surface and the lateral surface of the isolation structure. The conductive structure surrounds the isolation structure. The conductive structure is in contact with the first top surface of the isolation structure. A sidewall of a lower portion of the conductive structure is in contact with the isolation structure and extends beyond the second top surface of the isolation structure.

公开(公告)号：US20240244828A1

公开(公告)日：2024-07-18

申请号：US18155043

申请日：2023-01-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Heng WU

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/485

Abstract: A memory structure includes a semiconductor substrate, two word line structures, an isolation structure, and a bit line contact layer. The semiconductor substrate has a first trench, a second trench, a first top surface, and a second top surface adjoining the first and second trenches and lower than the first top surface. The two word line structures are respectively located in the first and second trenches. The isolation structure is located on the two word line structures and in contact with a sidewall of the first trench and a sidewall of the second trench, in which the isolation structure has a top surface extending to and coplanar with the second top surface of the semiconductor substrate. The bit line contact layer is located on the second top surface of the semiconductor substrate and surrounded by the isolation structure.