公开(公告)号：US10804184B2

公开(公告)日：2020-10-13

申请号：US16281360

申请日：2019-02-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a restraint layer, a plurality of contact plugs, and a plurality of through silicon vias. The restraint layer is disposed on the semiconductor substrate, and the contact plugs are inserted into the restraint layer. The through silicon vias extend from a bottom surface of the semiconductor substrate to a front surface opposite to the back surface and the through silicon vias are in contact with the contact plugs, respectively.

公开(公告)号：US10522466B1

公开(公告)日：2019-12-31

申请号：US16153073

申请日：2018-10-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/482 ,  H01L21/768 ,  H01L21/683 ,  H01L21/304 ,  H01L21/283

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.

公开(公告)号：US12283567B2

公开(公告)日：2025-04-22

申请号：US18604804

申请日：2024-03-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/00

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing an interconnection structure. The method also includes forming a first dielectric layer on the interconnection structure. The method further includes forming a sacrificial pattern on the first dielectric layer. The method also includes forming an RDL on the first dielectric layer and the sacrificial pattern. The method further includes removing the sacrificial pattern to form an air cavity within the RDL.

公开(公告)号：US12250808B2

公开(公告)日：2025-03-11

申请号：US18743453

申请日：2024-06-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Zhong Li ,  Hsih-Yang Chiu

IPC: H10B20/20

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

公开(公告)号：US12113046B2

公开(公告)日：2024-10-08

申请号：US18386345

申请日：2023-11-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Zhong Li ,  Yi-Ting Shih ,  Chien-Chung Wang ,  Hsih-Yang Chiu

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/48824 ,  H01L2224/85031 ,  H01L2224/85359

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

公开(公告)号：US11756988B2

公开(公告)日：2023-09-12

申请号：US16997954

申请日：2020-08-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L23/52 ,  H01L49/02 ,  H01L23/522 ,  H01G4/30

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L23/5223

Abstract: A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

公开(公告)号：US11676998B2

公开(公告)日：2023-06-13

申请号：US17568063

申请日：2022-01-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: G06F30/392 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0646 ,  H01L29/1095 ,  H01L29/6656

Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first well layer in the substrate and having a first electrical type, forming an isolation-mask layer on the first well layer, forming mask openings along the isolation-mask layer to expose portions of the first well layer, forming bottom conductive layers in the portions of the first well layer, forming a bias layer in the first well layer and spaced apart from the bottom conductive layers, forming first insulating layers on the bottom conductive layers, forming first conductive lines on the first insulating layers and parallel to each other. The bottom conductive layers have a second electrical type opposite to the first electrical type. The bottom conductive layers, the first insulating layers, the first conductive lines together configure programmable units.

公开(公告)号：US11646224B2

公开(公告)日：2023-05-09

申请号：US17538044

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/528

Abstract: The present disclosure provides a method of fabricating a semiconductor structure with a reduced pitch (half-pitch feature) and a method of fabricating the same. The method includes providing a substrate; forming a dielectric layer disposed on the substrate; forming at least one main feature disposed in the dielectric layer and contacting the substrate; forming at least one first conductive feature disposed in the dielectric layer and on the main feature; forming at least one first spacer interposed between the dielectric layer and a portion of the first conductive feature; forming a plurality of second conductive features disposed in the dielectric layer and on either side of the first conductive feature; and forming a plurality of second spacers interposed between the dielectric layer and portions of the second conductive features.

公开(公告)号：US11631656B2

公开(公告)日：2023-04-18

申请号：US17643177

申请日：2021-12-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu ,  Yi-Jen Lo

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

公开(公告)号：US11515388B2

公开(公告)日：2022-11-29

申请号：US17126609

申请日：2020-12-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: The present application discloses a semiconductor device with a P-N junction isolation structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first well layer positioned in the substrate and having a first electrical type, a bottom conductive layer positioned in the first well layer and having a second electrical type opposite to the first electrical type, a first insulating layer positioned on the bottom conductive layer, an isolation-mask layer positioned on the substrate and enclosing the first insulating layer, a first conductive line positioned on the first insulating layer, and a bias layer positioned in the first well layer and spaced apart from the bottom conductive layer. The bottom conductive layer, the first insulating layer, and the first conductive line together configure a programmable unit.