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    Manufacturing method of semiconductor device
    1.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US12278211B2

    公开(公告)日：2025-04-15

    申请号：US18491813

    申请日：2023-10-23

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Yi-Jen Lo ,  Hsih Yang Chiu ,  Ching Hung Chang ,  Chiang-Lin Shih

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

    Semiconductor structure and manufacturing method thereof
    3.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US11342307B2

    公开(公告)日：2022-05-24

    申请号：US16601575

    申请日：2019-10-14

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Hsih-Yang Chiu ,  Yi-Jen Lo

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

    Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

    Method for manufacturing semiconductor structure
    6.
    发明授权
    Method for manufacturing semiconductor structure 有权

    公开(公告)号：US11631656B2

    公开(公告)日：2023-04-18

    申请号：US17643177

    申请日：2021-12-07

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Hsih-Yang Chiu ,  Yi-Jen Lo

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

    Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

    Wafer-to-wafer interconnection structure and method of manufacturing the same
    8.
    发明授权
    Wafer-to-wafer interconnection structure and method of manufacturing the same 有权

    公开(公告)号：US11488840B2

    公开(公告)日：2022-11-01

    申请号：US17146438

    申请日：2021-01-11

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Yi-Jen Lo

    IPC: H01L23/48 ,  H01L23/52 ,  H01L21/48 ,  H01L23/498

    Abstract: A method of manufacturing a wafer-to-wafer interconnection structure includes forming a first etching stop layer with at least two portions on a first surface of a first substrate, and forming a void in one portion of the first etching stop layer. A second etching stop layer is formed on a first surface of a second substrate, and then the first surfaces of the first substrate and the second substrate are bonded, wherein the second etching stop layer is aligned to the void. By using the first and the second etching stop layers as etching stop layers, a first opening is formed from a second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV (through silicon via) is formed in the first opening, and a second TSV is formed in the second opening.

    Forming a self-aligned TSV with narrow opening in horizontal isolation layer interfacing substrate
    9.
    发明授权
    Forming a self-aligned TSV with narrow opening in horizontal isolation layer interfacing substrate 有权

    公开(公告)号：US11482474B2

    公开(公告)日：2022-10-25

    申请号：US17033904

    申请日：2020-09-27

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Yi-Jen Lo

    IPC: H01L23/48 ,  H01L21/768

    Abstract: A semiconductor device and method of manufacturing thereof are provided. The semiconductor device includes a substrate, a first dielectric layer, an isolation layer, a conductor and a liner layer. The substrate has a top surface and a bottom surface opposite the top surface. The first dielectric layer is on the bottom surface of the substrate, in which the first dielectric layer comprises an interconnect structure disposed therein. The isolation layer is on the top surface of the substrate. The conductor is disposed in the substrate and covers a portion of the isolation layer, in which the conductor includes a first portion connected to the interconnect structure and a second portion on the first portion, in which the first portion has a width greater than a width of the second portion. The liner layer is disposed between the substrate and the conductor.

    Semiconductor structure having hybrid bonding pad
    10.
    发明授权
    Semiconductor structure having hybrid bonding pad 有权

    公开(公告)号：US12293982B2

    公开(公告)日：2025-05-06

    申请号：US17839806

    申请日：2022-06-14

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Yi-Jen Lo

    IPC: H01L23/00

    Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a first semiconductor substrate, a first conductive pad, and a first hybrid bonding pad. The first conductive pad is over the first semiconductor substrate. The first hybrid bonding pad is on the first conductive pad. The first hybrid bonding pad includes nano-twins copper. A thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad.

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