公开(公告)号：US20240014127A1

公开(公告)日：2024-01-11

申请号：US17811067

申请日：2022-07-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L23/525 ,  H01L27/112

CPC classification number: H01L23/5252 ,  H01L27/11206 ,  H01L23/5256

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having an active area and forming a first diffusion area in the active area. The method also includes disposing a nitride layer on the active area and forming an opening in the nitride layer to expose the first diffusion area. The method also includes disposing an oxide layer in the opening to contact the first diffusion area.

公开(公告)号：US20230269935A1

公开(公告)日：2023-08-24

申请号：US17678407

申请日：2022-02-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

公开(公告)号：US20230180469A1

公开(公告)日：2023-06-08

申请号：US17541829

申请日：2021-12-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: The present application provides a method for manufacturing a semiconductor device including a merged active area (AA). The method includes forming a fuse gate structure over the active area; forming a device gate structure over the active area and adjacent to the fuse gate structure; and forming a contact plug coupled to the active area and extending away from the substrate. The fuse gate structure and the device gate structure are parallel and are formed over the active area.

公开(公告)号：US20240334687A1

公开(公告)日：2024-10-03

申请号：US18743453

申请日：2024-06-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H10B20/20

CPC classification number: H10B20/20

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

公开(公告)号：US20240014128A1

公开(公告)日：2024-01-11

申请号：US17858106

申请日：2022-07-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L23/525 ,  H01L27/112 ,  G11C17/16

CPC classification number: H01L23/5256 ,  H01L27/11206 ,  G11C17/165

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having an active area and a fuse component. The fuse component has a bottom electrode in the active area, a first dielectric layer on the active area and a top electrode on the first dielectric layer. The semiconductor device also includes a second dielectric layer on the active area and surrounding the first dielectric layer.

公开(公告)号：US20230180470A1

公开(公告)日：2023-06-08

申请号：US17543966

申请日：2021-12-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.

公开(公告)号：US20230069497A1

公开(公告)日：2023-03-02

申请号：US17465309

申请日：2021-09-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L29/06 ,  H01L29/08

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

公开(公告)号：US20230061312A1

公开(公告)日：2023-03-02

申请号：US17465328

申请日：2021-09-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  YI-TING SHIH ,  CHIEN-CHUNG WANG ,  HSIH-YANG CHIU

IPC: H01L23/00

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

公开(公告)号：US20220310633A1

公开(公告)日：2022-09-29

申请号：US17214494

申请日：2021-03-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L27/112

Abstract: The present application provides an anti-fuse one-time programmable (OTP) memory array and a manufacturing method of the anti-fuse one-time programmable (OTP) memory array. The memory array includes: active areas; pairs of programming word lines and read word lines; and dummy word lines. The active areas extend along a first direction in a semiconductor substrate, and are separately arranged along a second direction. The programming word lines, the read word lines and the dummy word lines extend along the second direction over the semiconductor substrate. A region in which a pair of programming word line and read word line are intersected with one of the active areas defines a unit cell in the memory array. The dummy word lines respectively lie between adjacent pairs of programming word lines and read word lines. A region in which one of the dummy word lines is intersected with one of the active areas defines an isolation transistor.