公开(公告)号：US20250071982A1

公开(公告)日：2025-02-27

申请号：US18238022

申请日：2023-08-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI

IPC: H10B20/25

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source/drain (S/D) region, and a resistance modification doped region. The well region is within the substrate with a first conductive type. The fuse medium is disposed over the substrate. The gate electrode is disposed over the fuse medium. The fuse doped region is under the gate electrode with a second conductive type different from first conductive type. The S/D region is adjacent to the fuse doped region with the second conductive type. The resistance modification doped region has the second conductive type and partially overlaps the fuse doped region.

公开(公告)号：US20240405064A1

公开(公告)日：2024-12-05

申请号：US18804340

申请日：2024-08-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L29/06 ,  H01L29/08

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

公开(公告)号：US20240063116A1

公开(公告)日：2024-02-22

申请号：US18209101

申请日：2023-06-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L23/525 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/08 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L29/42356 ,  H01L21/823481 ,  H01L29/41775 ,  H01L29/0847 ,  H01L27/088 ,  H01L21/823475 ,  H01L23/5283 ,  H01L21/823425

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

公开(公告)号：US20230269934A1

公开(公告)日：2023-08-24

申请号：US17678212

申请日：2022-02-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

公开(公告)号：US20230207453A1

公开(公告)日：2023-06-29

申请号：US17561151

申请日：2021-12-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/53295

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an inter-dielectric layer on a substrate; a conductive pad in the inter-dielectric layer; and a multi-stacking carrier structure including a first tier on the inter-dielectric layer, a second tier on the first tier, and a third tier on the second tier.

公开(公告)号：US20250125257A1

公开(公告)日：2025-04-17

申请号：US18991798

申请日：2024-12-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L23/525 ,  H01L23/528 ,  H10D62/13 ,  H10D64/23 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: The present disclosure provides a method of manufacturing semiconductor structure. The method includes providing a substrate, including an active area and an isolation surrounding the active area; forming a trench fuse in the active area; forming a gate structure of a transistor over the substrate adjacent to the trench fuse; and forming a doping region surrounding the trench fuse and the gate structure; wherein a distance between the isolation and the trench fuse is less than a distance between the isolation and the gate structure.

公开(公告)号：US20250071985A1

公开(公告)日：2025-02-27

申请号：US18511029

申请日：2023-11-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI

IPC: H10B20/25

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source/drain (S/D) region, and a resistance modification doped region. The well region is within the substrate with a first conductive type. The fuse medium is disposed over the substrate. The gate electrode is disposed over the fuse medium. The fuse doped region is under the gate electrode with a second conductive type different from first conductive type. The S/D region is adjacent to the fuse doped region with the second conductive type. The resistance modification doped region has the second conductive type and partially overlaps the fuse doped region.

公开(公告)号：US20240063115A1

公开(公告)日：2024-02-22

申请号：US17891421

申请日：2022-08-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L23/525 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L23/5256 ,  H01L23/5283 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/42356 ,  H01L27/088 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

公开(公告)号：US20230207452A1

公开(公告)日：2023-06-29

申请号：US17560548

申请日：2021-12-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L21/76802 ,  H01L21/76829

Abstract: A multi-stacking carrier structure includes an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer.

公开(公告)号：US20240063175A1

公开(公告)日：2024-02-22

申请号：US18386345

申请日：2023-11-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  YI-TING SHIH ,  CHIEN-CHUNG WANG ,  HSIH-YANG CHIU

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/85359 ,  H01L2224/85031 ,  H01L2224/04042 ,  H01L2224/03831 ,  H01L2224/48824

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).