公开(公告)号：US20220293561A1

公开(公告)日：2022-09-15

申请号：US17199458

申请日：2021-03-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo ,  Hsih Yang Chiu ,  Ching Hung Chang ,  Chiang-Lin Shih

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

公开(公告)号：US12266622B2

公开(公告)日：2025-04-01

申请号：US17840081

申请日：2022-06-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo

IPC: H01L21/00 ,  H01L23/00

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a first semiconductor substrate. The method also includes forming a first conductive pad over the first semiconductor substrate. The method further includes forming a first hybrid bonding pad on the first conductive pad, wherein the first hybrid bonding pad includes nano-twins copper, and a thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad.

公开(公告)号：US11610878B1

公开(公告)日：2023-03-21

申请号：US17465279

申请日：2021-09-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method includes providing a bottom substrate; bonding a first stacking chip and a second stacking chip onto the bottom substrate; conformally forming a first isolation layer to cover the first and second stacking chips and to at least partially fill a gap between the first and second stacking chips; performing a thinning process to expose back surfaces of the first and second stacking chips; performing a removal process to expose through substrate vias of the first and second stacking chips; forming a first capping layer to cover the through substrate vias of the first and second stacking chips; and performing a planarization process to expose the through substrate vias of the first and second stacking chips and provide a substantially flat surface.

公开(公告)号：US20220293552A1

公开(公告)日：2022-09-15

申请号：US17198252

申请日：2021-03-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo ,  Hsih Yang Chiu ,  Ching Hung Chang ,  Chiang-Lin Shih

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

公开(公告)号：US20220223433A1

公开(公告)日：2022-07-14

申请号：US17146438

申请日：2021-01-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo

IPC: H01L21/48 ,  H01L23/498

Abstract: A method of manufacturing a wafer-to-wafer interconnection structure includes forming a first etching stop layer with at least two portions on a first surface of a first substrate, and forming a void in one portion of the first etching stop layer. A second etching stop layer is formed on a first surface of a second substrate, and then the first surfaces of the first substrate and the second substrate are bonded, wherein the second etching stop layer is aligned to the void. By using the first and the second etching stop layers as etching stop layers, a first opening is formed from a second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV (through silicon via) is formed in the first opening, and a second TSV is formed in the second opening.

公开(公告)号：US10818508B2

公开(公告)日：2020-10-27

申请号：US16162729

申请日：2018-10-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo

IPC: H01L21/311 ,  H01L21/02

Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes steps of providing a stack structure, wherein the stack structure comprises a nitride layer, a first layer, a stop layer, a second layer, and a first oxide layer stacked in sequence; forming a third layer on the first oxide layer; patterning the third layer to obtain a line-and-space pattern comprising a plurality of first lines and a plurality of first spaces; forming a second oxide layer on the line-and-space pattern; removing the second oxide layer on the first lines; removing the first lines to form a plurality of second spaces; and etching the first oxide layer, the second layer, and the stop layer via the second spaces to form a plurality of second lines.

公开(公告)号：US10811382B1

公开(公告)日：2020-10-20

申请号：US16404830

申请日：2019-05-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Pei-Jhen Wu ,  Hsih-Yang Chiu ,  Chiang-Lin Shih ,  Ching-Hung Chang ,  Yi-Jen Lo

IPC: H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L21/321 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.