公开(公告)号：EP2871673A1

公开(公告)日：2015-05-13

申请号：EP13191736.1

申请日：2013-11-06

Applicant: NXP B.V.

Inventor： Yan, Liang ,  Daamen, Roel ,  Heringa, Anco ,  Hijzen, Erwin

IPC: H01L23/367 ,  H01L29/78 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L25/072 ,  H01L23/3677 ,  H01L27/0211 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7824 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract translation: 在具有多个单元电池的SOI功率器件中引入了集成散热器阵列，其可以用于降低温度上升以获得器件区域上的所有单元电池的更均匀的温度峰值，使得易于发生 可以避免故障，从而可以改善设备的安全操作区域。 此外阵列牺牲了更少的器件面积，因此导致低Rdson。

公开(公告)号：EP2806460B1

公开(公告)日：2020-01-01

申请号：EP14169718.5

申请日：2014-05-23

Applicant: NXP B.V.

Inventor： Dinh, Viet Thanh ,  Hurkx, Godefridus Antonius Maria ,  Vanhoucke, Tony ,  Slotboom, Jan Willem ,  Heringa, Anco ,  Zahariev, Ivan ,  Gridelet, Evelyne

IPC: H01L29/40 ,  H01L29/732 ,  H03F3/20

公开(公告)号：EP2879182A1

公开(公告)日：2015-06-03

申请号：EP13194868.9

申请日：2013-11-28

Applicant: NXP B.V.

Inventor： Dinh, Viet Thanh ,  Vanhoucke, Tony ,  Gridelet, Evelyne ,  Heringa, Anco ,  Slotboom, Jan Willem ,  Klaassen, Dirk

IPC: H01L29/735 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L29/7371 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/735 ,  H01L29/7378 ,  H01L29/7809 ,  H01L29/7835

Abstract: Disclosed is a transistor (100, 200, 300) having a first region (120, 320) of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region (140, 340) of the first conductivity type having a portion (142, 342) including a contact terminal (145, 345) for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region (130, 330) of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate (110) having a doped region (112) of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal (115) connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

Abstract translation: 公开了具有第一导电类型的第一区域（120,320）用于将电荷载流子注入晶体管的晶体管（100,200,300）和具有第一导电类型的横向延伸的第二区域（140,340），其具有 包括用于从所述晶体管排出所述电荷载流子的接触端子（145,345）的部分（142,342），其中所述第一区域与所述第二区域分隔开限定第二导电类型的中间区域（130,330） 第一pn结与第一区域和与第二区域的第二pn结，其中横向延伸区域将该部分与第二pn结分离，并且其中该晶体管还包括具有掺杂区域（112）的衬底（110） 所述第二导电类型，所述掺杂区域沿着所述横向延伸的第二区域接触并延伸;以及另外的接触端子（115），其连接到所述掺杂区域以排出少数电荷载体 来自横向延伸的第二区域。 还公开了包括这种晶体管的放大器电路和IC。

公开(公告)号：EP2871672A1

公开(公告)日：2015-05-13

申请号：EP13191727.0

申请日：2013-11-06

Applicant: NXP B.V.

Inventor： Yan, Liang ,  Daamen, Roel ,  Heringa, Anco ,  Hijzen, Erwin

IPC: H01L23/367 ,  H01L27/02 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L23/3677 ,  H01L27/0211 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7824 ,  H01L2924/0002 ,  H05K7/20 ,  H01L2924/00

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract translation: 在具有多个单元电池的SOI功率器件中引入了集成散热器阵列，其可以用于降低温度上升，从而在整个器件区域上为所有单元电池获得更均匀的温度峰值，使得易于 可以避免故障，从而可以提高设备的安全工作面积。 此外，阵列牺牲了较少的器件面积，因此导致低Rdson。

公开(公告)号：EP2746799A1

公开(公告)日：2014-06-25

申请号：EP12198395.1

申请日：2012-12-20

Applicant: NXP B.V.

Inventor： Zieren, Victor ,  Heringa, Anco ,  Wunnicke, Olaf ,  Slotboom, Jan ,  van Veldhoven, Robert ,  Claes, Jan

IPC: G01R33/06 ,  H01L29/82

CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

Abstract: A semiconductor magnetic field sensor includes a semiconductor well (PW) on top of a semiconductor layer (Pepi). An insulation layer (ISO2) is located between the semiconductor layer (Pepi) and the substrate (SUB). The semiconductor well (PW) contains a lateral NPN bipolar magnetotransistor having two base contact regions (5) and (10) contacting the semiconductor well (PW). The semiconductor well (PW) further comprises two heavily n-type doped regions acting as collector regions (20) and (25) for the lateral NPN bipolar magnetotransistor. The semiconductor well (PW) further comprises a heavily doped n-type region acting as an emitter region (15) for the lateral NPN bipolar magnetotransistor and placed in between the two collector regions (20) and (25). A first MOS structure, having a first gate terminal (G 1 ), is located between the first collector region (20) and the emitter region (15). A second MOS structure, having a second gate terminal (G 2 ), is located between the emitter region (15) and the second collector region (25). By having the emitter region (15) placed between the first and the second collector regions (20) and (25), and by having properly biased MOS structures between the emitter region (15) and the collector regions (20) and (25), a first and a second collector current flowing in the semiconductor well (PW) generated during operation of the semiconductor magnetic field sensor are deflected down in a perpendicular direction from a plane defined by a surface (S) of the semiconductor magnetic field sensor and parallel to a direction of the magnetic field (B x ). The increase of the effective vertical deflection (L eff ) of the collector currents enhances the response of the semiconductor magnetic field sensor to an applied magnetic field (B x ) for a given emitter input bias current thus sensing with better accuracy also small values of the applied magnetic field (B x ). Furthermore the use of MOS structures ensures clean interfaces between the emitter region (15), the collector regions (20) and (25) and the MOS structures, avoiding the formation of material imperfections, defects, or interface states that cause an imbalance in the first and the second collector currents even in absence of a magnetic field (B x ).

Abstract translation: 半导体磁场传感器包括在半导体层（Pepi）顶部的半导体阱（PW）。 绝缘层（ISO2）位于半导体层（Pepi）和衬底（SUB）之间。 半导体阱（PW）包含具有与半导体阱（PW）接触的两个基极接触区域（5）和（10）的侧向NPN双极性磁电晶体管。 半导体阱（PW）还包括用作横向NPN双极型磁晶体管的集电极区域（20）和（25）的两个重的n型掺杂区域。 半导体阱（PW）还包括用作横向NPN双极型磁电晶体管的发射极区域（15）的重掺杂n型区域，并放置在两个集电极区域（20）和（25）之间。 具有第一栅极端子（G 1）的第一MOS结构位于第一集电极区域（20）和发射极区域（15）之间。 具有第二栅极端子（G 2）的第二MOS结构位于发射极区域（15）和第二集电极区域（25）之间。 通过使发射极区域（15）放置在第一和第二集电极区域（20）和（25）之间，并且通过在发射极区域（15）和集电极区域（20）和（25）之间具有适当偏置的MOS结构， 在半导体磁场传感器的工作过程中产生的在半导体阱（PW）中流动的第一和第二集电极电流从由半导体磁场传感器的表面（S）限定的平面沿垂直方向向下偏转并且平行 朝向磁场（B x）的方向。 集电极电流的有效垂直偏转（L eff）的增加增强了半导体磁场传感器对给定发射极输入偏置电流的施加磁场（B x）的响应，从而以更好的精度检测到较小的值 施加磁场（B x）。 此外，使用MOS结构确保发射极区域（15），集电极区域（20）和（25）与MOS结构之间的清洁界面，避免形成导致不平衡的材料缺陷，缺陷或界面状态 第一和第二集电极电流即使没有磁场（B x）。

公开(公告)号：EP2741330A1

公开(公告)日：2014-06-11

申请号：EP12195904.3

申请日：2012-12-06

Applicant: NXP B.V.

Inventor： Reimann, Klaus ,  Ritter, Hans-Martin ,  Schnitt, Wolfgang ,  Heringa, Anco

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0255

Abstract: An ESD protection circuit comprises a series connection of at least two protection components between a signal line to be protected and a return line (e.g. ground), comprising a first protection component connected to the signal line and a second protection component connected to the ground line. They are connected with opposite polarity so that when one conducts in forward direction the other conducts in reverse breakdown mode. A bias voltage source connects to the junction between the two protection components through a bias impedance. The use of the bias voltage enables the signal distortions resulting from the ESD protection circuit to be reduced.

Abstract translation: ESD保护电路包括在待保护的信号线和返回线（例如接地）之间的至少两个保护部件的串联连接，包括连接到信号线的第一保护部件和连接到接地线的第二保护部件 。 它们以相反的极性连接，使得当一个正向导通时，另一个导通反向击穿模式。 偏置电压源通过偏置阻抗连接到两个保护元件之间的接点。 使用偏置电压可以降低由ESD保护电路产生的信号失真。

公开(公告)号：EP2720270A1

公开(公告)日：2014-04-16

申请号：EP13185012.5

申请日：2013-09-18

Applicant: NXP B.V.

Inventor： Heringa, Anco ,  Koops, Gerhard ,  Boksteen, Boni, Kofi ,  Ferrara, Alessandro

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/404 ,  H01L29/7835 ,  H01L29/78624

Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

Abstract translation: 描述半导体器件，包括半导体器件和驱动电路的电路的实施例，以及用于操作半导体器件的方法。 在一个实施例中，半导体器件包括在衬底中形成的衬底，源极区，漏极区和漏极延伸区以及与漏极延伸区相邻的绝缘层。 绝缘层内部和之上形成栅极层和场板。 场板位于漏极延伸区域附近，并且与栅极层和源极区域电绝缘，使得电压可以独立于施加到栅极层和源极区域的电压施加到场板。 还描述了其他实施例。

公开(公告)号：EP2469289A1

公开(公告)日：2012-06-27

申请号：EP11194304.9

申请日：2011-12-19

Applicant: NXP B.V.

Inventor： Curatola, Gilberto ,  Zieren, Victor ,  Heringa, Anco

IPC: G01R33/06 ,  H01L27/22

CPC classification number: G01R33/06 ,  G01R33/066 ,  H01L27/22 ,  H01L29/82 ,  H01L43/00

Abstract: A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals.

Abstract translation: 场效应磁传感器有助于高灵敏度的磁场检测。 根据一个或多个示例性实施例，分别在第一和第二源极/漏极端子与第三源极/漏极端子之间的电流分别通过用于第一和第二端子中的每一个的单独沟道区域中的反转层进行控制。 响应于磁场，相对于在第三源极/漏极端子和第二源极/漏极端子之间通过的电流量，在第三源极/漏极端子与第一和第二源极/漏极端子中的一个之间传递更大量的电流 第一和第二源极/漏极端子之一。