公开(公告)号：CA2351327A1

公开(公告)日：2000-06-15

申请号：CA2351327

申请日：1999-12-03

Applicant: QUALCOMM INC

Inventor： PERSICO CHARLES K ,  APARIN VLADIMIR

IPC: H03F1/32 ,  H03H11/28

Abstract: Techniques to reduce intermodulation distortion at the output of an active circuit having even-order and odd-order nonlinearities. The IM3 products generated by the even-order nonlinearity of the active circuit are canceled against the IM3 products generated by the odd-order nonlinearity. The amplitude and phase of the IM3 products can be manipulated by adjusting eith er the source or load impedance, or both, of the active circuit. The amplitude and phase of the IM2 products generated by the even-order nonlinearity can b e manipulated by adjusting the impedance of the active circuit at subharmonic and second harmonic frequencies (i.e., the frequencies of the IM2 products). By properly tuning or "matching" the impendance of either the source or load , or both, of the active circuit at either the sub-harmonic or second harmonic frequency, or both, the amplitude and phase of the IM2 products can be adjusted such that the IM3 products resulting from the even-order nonlineari ty approximately cancel the IM3 product.

公开(公告)号：FI19992295A

公开(公告)日：2000-01-21

申请号：FI19992295

申请日：1999-10-22

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03F3/45 ,  H03H11/22 ,  H03H

Abstract: An active phase splitter comprises two or more phase shift circuits. Each phase shift circuit comprises a number of active devices and capacitors. For a single-pole active phase splitter, within each phase shift circuit, two active devices are configured as a cascode amplifier. The first active device is configured as a common source amplifier and the second active device is configured as a common gate amplifier. A capacitor is connected across the gate and drain of the first active device to generates the necessary pole-zero pair for the phase shift circuit. The cascode configuration results in the desired transfer function and provides transconversion of voltage input to current outputs. Active phase splitters with two or more poles can be built using the same inventive concept.

公开(公告)号：AU7692598A

公开(公告)日：1998-12-11

申请号：AU7692598

申请日：1998-05-21

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03F3/45 ,  H03H11/22

Abstract: An active phase splitter comprises two or more phase shift circuits. Each phase shift circuit comprises a number of active devices and capacitors. For a single-pole active phase splitter, within each phase shift circuit, two active devices are configured as a cascode amplifier. The first active device is configured as a common source amplifier and the second active device is configured as a common gate amplifier. A capacitor is connected across the gate and drain of the first active device to generates the necessary pole-zero pair for the phase shift circuit. The cascode configuration results in the desired transfer function and provides transconversion of voltage input to current outputs. Active phase splitters with two or more poles can be built using the same inventive concept.

公开(公告)号：RU2436229C2

公开(公告)日：2011-12-10

申请号：RU2009139083

申请日：2008-03-21

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H04B1/52

Abstract: Изобретениеотноситсяк техникесвязии описываетметодысокращениянеблагоприятныхвоздействийпросачиванияпередаваемого (ТХ) сигналав системедуплекснойбеспроводнойсвязи. Вчастности, описанметодсокращениянеблагоприятныхвоздействийискажениявторогопорядкаотпросачиванияТХсигнала. Техническийрезультатсостоитв уменьшенииилиустраненииискажениявторогопорядкаотпросачиванияпередаваемогосигнала. Дляэтогобеспроводноеустройствовозводитв квадратобъединенныйсигнал, которыйнесети полезный RX сигнал, иТХсигналпросачивания. Например, устройствоможетвключатьв себяустройство, котороедемонстрируетсильнуюнелинейностьвторогопорядка, чтобы, посуществу, возводитьв квадратобъединенныйсигнал. Устройствовычитаетвозведенныйв квадратсигнализвыходногосигналасмесителяв приемномтракте, нейтрализуяпоменьшеймеречастьискажениявторогопорядка, вызываемогосмесителем. Такимобразом, устройствоможетуменьшатьнеблагоприятныевоздействияискажениявторогопорядкаотпросачиванияТХсигналаи, такимобразом, усиливатьилиподдерживатьчувствительностьприемника. 5 н. и 21 з.п. ф-лы, 8 ил.

公开(公告)号：BR0115061A

公开(公告)日：2005-06-28

申请号：BR0115061

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR ,  SHAH PETER J

IPC: H03F1/32 ,  H03F1/34 ,  H03F3/19 ,  H05F3/00

Abstract: A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor. In accordance with the inventive teachings, the buffer has a low gain and high output impedance at first frequency (f1) of a first signal applied to the circuit and a second frequency (f2) of a second signal applied to the circuit and a unity gain and low output impedance a difference between the first and second frequencies. In another specific embodiment, the inductor is inserted between the output of the unity gain buffer and the input terminal of the transistor. In alternative embodiments, circuitry is shown for providing a direct current offset at the input of the transistor. As another alternative, the linearization circuit consists of series inductor and capacitor connected between the common and input terminals of the transistor. In yet another embodiment, the linearization circuit consists of the first and the second series inductor and capacitor circuits. The first series LC circuit is connected between the common terminal of the transistor and ground and the second series LC circuit is connected between the input terminal of the transistor and ground.

公开(公告)号：AU2003287409A1

公开(公告)日：2004-06-07

申请号：AU2003287409

申请日：2003-10-30

Applicant: QUALCOMM INC

Inventor： WU YUE ,  APARIN VLADIMIR

IPC: H03B5/08 ,  H03B5/12

Abstract: A self-biased voltage controlled oscillator (VCO) that includes a VCO core including a plurality of switching transistors, a resonant tank circuit operatively coupled to the VCO core, a current source operatively coupled to the VCO core for supplying a bias current to the VCO core, and a biasing circuit operatively coupled to both the resonant tank circuit and to the current source. The biasing circuit and the switching transistors of the VCO core cooperatively function to bias the current source, whereby the VCO is self-biased.

公开(公告)号：AU759831B2

公开(公告)日：2003-05-01

申请号：AU2726500

申请日：2000-01-13

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03H7/42 ,  H03F3/45 ,  H03H11/32

Abstract: Many applications require the conversion of a differential current signal into a single-ended signal. The shortcomings encountered with existing approaches include poor conversion efficiency, limited bandwidth, and large size. The converter disclosed uses active devices to obtain a unit of small size and high efficiency having a wide bandwidth of operation.

公开(公告)号：AU2002307386A1

公开(公告)日：2002-11-05

申请号：AU2002307386

申请日：2002-04-17

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03F1/30 ,  H03F1/00 ,  H03F1/32

Abstract: The present invention provides a technique for selective cancellation of the 2nd-order or 3rd-order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function is such that, at a particular bias voltage, nonlinearity is zero. The invention provides a bias circuit that generates the optimum bias voltage for a transistor at which its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. The currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity. A feedback circuit senses the DC signal and generates the bias voltages of the bias transistors that force the DC signal to be zero. One of the bias voltages is applied to the main transistor resulting in cancellation of its selected nonlinearity. The system may be readily implemented using the integrated circuit technology such that the transistors of the bias circuit are closely matched to each other and to the main transistor. The distortion cancellation effect provided by the present invention exhibits low sensitivity to variations in the transistor processing and operational temperature.

公开(公告)号：ID30156A

公开(公告)日：2001-11-08

申请号：ID20011751

申请日：2000-01-13

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03H7/42 ,  H03F3/45 ,  H03H11/32

Abstract: Many applications require the conversion of a differential current signal into a single-ended signal. The shortcomings encountered with existing approaches include poor conversion efficiency, limited bandwidth, and large size. The converter disclosed uses active devices to obtain a unit of small size and high efficiency having a wide bandwidth of operation.

公开(公告)号：NO20013482A

公开(公告)日：2001-09-14

申请号：NO20013482

申请日：2001-07-13

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03H7/42 ,  H03F3/45 ,  H03H11/32 ,  H03F

CPC classification number: H03F3/45071