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公开(公告)号：DE69939750D1
公开(公告)日：2008-11-27
申请号：DE69939750
申请日：1999-07-27
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES
Abstract: A hardware-efficient transceiver. The transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal A digital-to-analog converter converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. In the transceiver implementation, the digital circuit upconverts a first transmit signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmit signal in response thereto. A second circuit is provided for converting the digital transmit signal to an analog transmit signal. Transmit and receive circuitry are provided for transmitting the analog transmit signal and receiving an analog receive signal, respectively. In a specific embodiment, the analog receive signal is digitally downconverted to provide a digital receive signal in response to a second periodic signal. A significant feature of the invention resides in the provision of the first and second periodic signals with a single local oscillator. A direct digital synthesizer is included for generating one of the reference signals from the output of the local oscillator. The transmit circuit includes a delta-sigma digital-to-analog converter having the first periodic signal as an input The delta-sigma digital-to-analog converter has a low-bit digital-to-analog converter and a delta-sigma modulator. In the illustrative embodiment, the low-bit digital-to-analog converter is a 1-bit digital-to-analog converter and the delta-sigma modulator is a sixth order delta-sigma modulator. The delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.
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公开(公告)号：BR9911733A
公开(公告)日：2001-04-03
申请号：BR9911733
申请日：1999-06-29
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES , GILMORE ROBERT P
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公开(公告)号：AU759608B2
公开(公告)日：2003-04-17
申请号：AU5323299
申请日：1999-07-27
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES
Abstract: A hardware-efficient transceiver. The transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal A digital-to-analog converter converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. In the transceiver implementation, the digital circuit upconverts a first transmit signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmit signal in response thereto. A second circuit is provided for converting the digital transmit signal to an analog transmit signal. Transmit and receive circuitry are provided for transmitting the analog transmit signal and receiving an analog receive signal, respectively. In a specific embodiment, the analog receive signal is digitally downconverted to provide a digital receive signal in response to a second periodic signal. A significant feature of the invention resides in the provision of the first and second periodic signals with a single local oscillator. A direct digital synthesizer is included for generating one of the reference signals from the output of the local oscillator. The transmit circuit includes a delta-sigma digital-to-analog converter having the first periodic signal as an input The delta-sigma digital-to-analog converter has a low-bit digital-to-analog converter and a delta-sigma modulator. In the illustrative embodiment, the low-bit digital-to-analog converter is a 1-bit digital-to-analog converter and the delta-sigma modulator is a sixth order delta-sigma modulator. The delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.
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公开(公告)号：AU758094B2
公开(公告)日：2003-03-13
申请号：AU2182100
申请日：1999-12-14
Applicant: QUALCOMM INC
Inventor： YOUNIS SAED G , BUTTERFIELD DANIEL KEYES
IPC: H03M3/02
Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention eliminates the clock jitter disadvantage between sampled-data and Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter preferably includes at least two switches and a capacitor. A first switch is used to charge the capacitor and a second switch is used to discharge the capacitor. Each switch is controlled by a clock phase wherein the sum of the two phases equals the clock duty cycle.
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15.发明专利
公开(公告)号：HK1042174A1
公开(公告)日：2002-08-02
申请号：HK02103874
申请日：2002-05-23
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES
Abstract: A hardware-efficient transceiver. The transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal A digital-to-analog converter converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. In the transceiver implementation, the digital circuit upconverts a first transmit signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmit signal in response thereto. A second circuit is provided for converting the digital transmit signal to an analog transmit signal. Transmit and receive circuitry are provided for transmitting the analog transmit signal and receiving an analog receive signal, respectively. In a specific embodiment, the analog receive signal is digitally downconverted to provide a digital receive signal in response to a second periodic signal. A significant feature of the invention resides in the provision of the first and second periodic signals with a single local oscillator. A direct digital synthesizer is included for generating one of the reference signals from the output of the local oscillator. The transmit circuit includes a delta-sigma digital-to-analog converter having the first periodic signal as an input The delta-sigma digital-to-analog converter has a low-bit digital-to-analog converter and a delta-sigma modulator. In the illustrative embodiment, the low-bit digital-to-analog converter is a 1-bit digital-to-analog converter and the delta-sigma modulator is a sixth order delta-sigma modulator. The delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.
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Patent Agency Ranking
公开(公告)号：CA2354623C
公开(公告)日：2008-10-07
申请号：CA2354623
申请日：1999-12-14
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES , YOUNIS SAED G
Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter (15) using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter (17) that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter (17) preferably includes at least two switches and a capacitor (28).
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公开(公告)号：CA2338539A1
公开(公告)日：2000-02-10
申请号：CA2338539
申请日：1999-07-27
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES
Abstract: A hardware-efficient transceiver. The transceiver (80) includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direc t digital synthesizer (84) provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter converts (82) the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal.
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公开(公告)号：AU4726099A
公开(公告)日：2000-01-17
申请号：AU4726099
申请日：1999-06-29
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES , GILMORE ROBERT P
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公开(公告)号：CA2336383A1
公开(公告)日：2000-01-06
申请号：CA2336383
申请日：1999-06-29
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P , BUTTERFIELD DANIEL KEYES
Abstract: In the illustrative embodiment, the inventive system includes a low-bit digital-to-analog converter (68) for converting a first signal at a referenc e frequency to a digital signal. A delta-sigma converter is included for suppressing noise in the digital signal within the predetermined range of th e reference frequency and providing a noise-shaped signal in response thereto. A bandpass filter (72) filters out the out-of-band noise and provides an accurate periodic signal which lacks glitch noise. In a particular embodimen t, the inventive system further includes a direct digital synthesizer (42) for providing the first signal at the first frequency and the accurate reference periodic signal is supplied as reference signal to a phase-locked loop (50).
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20.发明申请HARDWARE-EFFICIENT TRANSCEIVER WITH DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER 审中-公开具有DELTA-SIGMA数字到模拟转换器的硬件有效收发器
公开(公告)号：WO0007301A2
公开(公告)日：2000-02-10
申请号：PCT/US9917081
申请日：1999-07-27
Applicant: QUALCOMM INC
Inventor： BUTTERFIELD DANIEL KEYES
CPC classification number: H03F3/24 , H03F2200/331 , H04B1/40
Abstract: A hardware-efficient transceiver. The transceiver (80) includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer (84) provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter converts (82) the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal.
Abstract translation: 硬件高效的收发器。 收发器（80）包括用于将基带信号转换成中频信号的数字电路。 信号源提供第一频率的第一周期信号。 直接数字合成器（84）从第一周期性参考信号提供第二频率的第二周期信号。 上变频器电路使用第二周期信号将基带信号数字上变频到数字中频信号。 数模转换器使用第一周期信号将（82）数字中频信号转换成模拟中频信号。
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