公开(公告)号：ES2519566T3

公开(公告)日：2014-11-07

申请号：ES10740813

申请日：2010-07-30

Applicant: QUALCOMM INC

Inventor： MARRA THOMAS D ,  HADJICHRISTOS ARISTOTELE ,  PLETCHER NATHAN M

IPC: H03F3/04 ,  H03F1/30 ,  H03F3/189

Abstract: Un aparato de ajuste de la polarización, que comprende: un medio para obtener una medición de una tensión desarrollada en los bordes de una resistencia parásita de un inductor (214) acoplado a al menos un transistor (212) de un amplificador (210); y un medio para generar al menos una tensión de polarización de entrada para el al menos un transistor (212) del amplificador (210) en base a la medición para obtener una corriente de polarización de blanco con destino al amplificador (210).

公开(公告)号：WO2011022549A3

公开(公告)日：2011-04-21

申请号：PCT/US2010046021

申请日：2010-08-19

Applicant: QUALCOMM INC ,  ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

Inventor： ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

IPC: H03H7/38 ,  H03F1/42 ,  H03F3/00 ,  H03F3/193

CPC classification number: H03F1/42 ,  H03F1/223 ,  H03F3/193 ,  H03F2200/318 ,  H03H7/40

Abstract: A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.

Abstract translation: 描述了可以提高性能的可调谐级间匹配电路。 在示例性设计中，装置包括耦合在第一和第二有源电路之间的第一有源电路（例如，驱动器放大器），第二有源电路（例如，功率放大器）和可调谐级间匹配电路。 可调谐级间匹配电路包括可以在离散步骤中变化的可调谐电容器，以调整第一和第二有源电路之间的阻抗匹配。 在示例性设计中，可调谐电容器包括（i）并联耦合的多个电容器和（ii）耦合到多个电容器的多个开关，用于每个电容器的一个开关。 每个开关可以被接通以选择一个相关联的电容器或关闭以取消选择相关联的电容器。 可调谐电容器还可以包括与多个电容器并联耦合的固定电容器。

公开(公告)号：WO2011008562A2

公开(公告)日：2011-01-20

申请号：PCT/US2010040488

申请日：2010-06-29

Applicant: QUALCOMM INC ,  KLEMENS GUY ,  MYERS THOMAS A ,  FREDERICK JR NORMAN L ,  ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

Inventor： KLEMENS GUY ,  MYERS THOMAS A ,  FREDERICK JR NORMAN L ,  ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

IPC: H01L23/64 ,  H03F3/195

CPC classification number: H03F3/195 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6655 ,  H01L2223/6661 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/19015 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.

Abstract translation: 这里描述了紧凑的集成功率放大器。 在示例性设计中，装置包括（i）具有用于功率放大器的至少一个晶体管的集成电路（IC）管芯，以及（ii）具有用于功率放大器的负载电感器的IC封装。 IC芯片安装在IC封装上，晶体管位于负载感应器上方。 在示例性设计中，IC管芯包括放置在IC封装上的负载电感器上的晶体管歧管。 晶体管制造在晶体管歧管中，在晶体管歧管的中心具有漏极连接，并且在晶体管歧管的两侧具有源极连接。 IC芯片和IC封装可以包括一个或多个附加的功率放大器。 每个功率放大器的晶体管可以位于该功率放大器的负载电感上。

公开(公告)号：WO2014078742A3

公开(公告)日：2014-07-03

申请号：PCT/US2013070434

申请日：2013-11-15

Applicant: QUALCOMM INC

Inventor： CHA JEONGWON ,  LEE CHANG-HO ,  HADJICHRISTOS ARISTOTELE

IPC: H03F1/02 ,  H03F1/22 ,  H03F1/52 ,  H03F3/21 ,  H03K17/10

CPC classification number: H03F1/0277 ,  H03F1/223 ,  H03F1/523 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/61 ,  H03K17/102

Abstract: Techniques for providing adjustable gain in an amplifier. In an aspect, a composite amplifier having adjustable gain includes a plurality of amplifiers coupled in parallel, wherein each of the amplifiers may be turned on or off to adjust the overall gain of the composite amplifier. Each amplifier may include an input transistor and at least two cascode transistors. To turn each amplifier off, the gate voltage of a second or lowermost cascode transistor coupled to the input transistor may be grounded, and the gate voltage of a first cascode transistor coupled to the output voltage may be coupled to a first turn-off voltage to reduce the drain-to-gate voltage drop across the first cascode transistor. Further aspects provide for decoupling a capacitor coupled to the gates of the cascode transistors from AC ground when the amplifier is turned off.

Abstract translation: 在放大器中提供可调增益的技术。 在一方面，具有可调增益的复合放大器包括并联耦合的多个放大器，其中每个放大器可被导通或关断以调整复合放大器的总体增益。 每个放大器可以包括输入晶体管和至少两个共源共栅晶体管。 为了关闭每个放大器，耦合到输入晶体管的第二或最低共源共栅晶体管的栅极电压可以接地，并且耦合到输出电压的第一共源共栅晶体管的栅极电压可以耦合到第一截止电压到 降低跨越第一共源共栅晶体管的漏极 - 栅极电压降。 另外的方面提供了当放大器关闭时将耦合到共源共栅晶体管的栅极的电容器与AC地耦合的去耦合。

公开(公告)号：WO2010141774A3

公开(公告)日：2012-01-26

申请号：PCT/US2010037322

申请日：2010-06-03

Applicant: QUALCOMM INC ,  SEE PUAY HOE ,  HADJICHRISTOS ARISTOTELE ,  SAHOTA GURKANWAL SINGH

Inventor： SEE PUAY HOE ,  HADJICHRISTOS ARISTOTELE ,  SAHOTA GURKANWAL SINGH

IPC: H04B1/04

CPC classification number: H04B1/0458 ,  H03F1/565 ,  H03F3/24 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2203/7209

Abstract: Tunable matching circuits for power amplifiers are described. In an exemplary design, an apparatus may include a power amplifier and a tunable matching circuit. The power amplifier may amplify an input RF signal and provide an amplified RF signal. The tunable matching circuit may provide output impedance matching for the power amplifier, may receive the amplified RF signal and provide an output RF signal, and may be tunable based on at least one parameter effecting the operation of the power amplifier. The parameter(s) may include an envelope signal for the amplified RF signal, an average output power level of the output RF signal, a power supply voltage for the power amplifier, IC process variations, etc. The tunable matching circuit may include a series variable capacitor and/or a shunt variable capacitor. Each variable capacitor may be tunable based on a control generated based on the parameter(s).

Abstract translation: 描述了用于功率放大器的可调谐匹配电路。 在示例性设计中，设备可以包括功率放大器和可调谐匹配电路。 功率放大器可以放大输入RF信号并提供放大的RF信号。 可调谐匹配电路可以为功率放大器提供输出阻抗匹配，可以接收放大的RF信号并提供输出RF信号，并且可以基于影响功率放大器的操作的至少一个参数来调节。 参数可以包括放大的RF信号的包络信号，输出RF信号的平均输出功率电平，功率放大器的电源电压，IC过程变化等。可调谐匹配电路可以包括一系列 可变电容器和/或分流可变电容器。 每个可变电容器可以基于基于参数产生的控制来调节。

公开(公告)号：WO2011014849A3

公开(公告)日：2011-06-23

申请号：PCT/US2010044033

申请日：2010-07-30

Applicant: QUALCOMM INC ,  MARRA THOMAS D ,  HADJICHRISTOS ARISTOTELE ,  PLETCHER NATHAN M

Inventor： MARRA THOMAS D ,  HADJICHRISTOS ARISTOTELE ,  PLETCHER NATHAN M

IPC: H03F1/30 ,  H03F3/189

CPC classification number: H03F1/301 ,  H03F1/30 ,  H03F3/04 ,  H03F3/189

Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

Abstract translation: 描述了用于监视和控制放大器的偏置电流的技术。 在示例性设计中，装置可以包括放大器和偏置电路。 放大器可以包括耦合到电感器的至少一个晶体管。 偏置电路可以产生用于放大器中的至少一个晶体管的至少一个偏置电压以获得放大器的目标偏置电流。 偏置电路可基于放大器中的电感器两端的电压或通过与放大器中的至少一个晶体管中的一个晶体管形成的电流镜的电流或者栅极至源极电压来生成至少一个偏置电压 放大器中的至少一个晶体管中的一个晶体管的电压，或复制放大器的复制电路中的电压，或者禁用开关模式电源而施加于放大器的电流。

公开(公告)号：WO2010148407A3

公开(公告)日：2011-02-24

申请号：PCT/US2010039376

申请日：2010-06-21

Applicant: QUALCOMM INC ,  SEE PUAY HOE ,  BALLANTYNE GARY JOHN ,  SAHOTA GURKANWAL SINGH ,  HADJICHRISTOS ARISTOTELE ,  CICALINI ALBERTO

Inventor： SEE PUAY HOE ,  BALLANTYNE GARY JOHN ,  SAHOTA GURKANWAL SINGH ,  HADJICHRISTOS ARISTOTELE ,  CICALINI ALBERTO

IPC: H04B1/04

CPC classification number: H04B1/0458 ,  H03H7/40

Abstract: Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.

Abstract translation: 所公开的示例性实施例涉及可用于测量功率和/或阻抗的功率和阻抗测量电路。 测量电路可以包括传感器和计算单元。 传感器可以感测（i）跨耦合到负载的串联电路的第一电压信号以获得第一感测信号，以及（ii）串联电路的指定端的第二电压信号以获得第二感测信号。 传感器可以将（i）第一感测信号的第一版本与第二感测信号的第一版本混合以获得第一传感器输出，以及（ii）第一感测信号的第二版本，具有第二感测的第二版本 信号以获得第二传感器输出。 计算单元可以基于传感器输出来确定串联电路的指定端处的阻抗和/或传递功率。

公开(公告)号：WO2011031540A2

公开(公告)日：2011-03-17

申请号：PCT/US2010046915

申请日：2010-08-27

Applicant: QUALCOMM INC ,  SU WENJUN ,  HADJICHRISTOS ARISTOTELE ,  CASSIA MARCO ,  NARATHONG CHIEWCHARN

Inventor： SU WENJUN ,  HADJICHRISTOS ARISTOTELE ,  CASSIA MARCO ,  NARATHONG CHIEWCHARN

IPC: G01R19/04

CPC classification number: G01R19/04

Abstract: A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.

Abstract translation: 描述具有可变偏置电流和/或可变偏置电压的高线性快速峰值检测器。 在示例性设计中，峰值检测器包括晶体管，可变电流源，电容器和反馈电路。 晶体管接收输入信号并提供源极电流。 可变电流源接收输入信号，当输入信号为低电平时提供高偏置电流，并且当输入信号为高电平时提供低偏置电流。 当输入信号为高电平时，电容器由电源电流充电，当输入信号为低电平时，电容器被高偏置电流放电。 当输入信号为高电平时，反馈电路接收来自电容器的检测信号，并为晶体管提供更高的偏置电压，这导致来自晶体管的较高的源极电流。

公开(公告)号：WO2009061835A2

公开(公告)日：2009-05-14

申请号：PCT/US2008082504

申请日：2008-11-05

Applicant: QUALCOMM INC ,  CASSIA MARCO ,  HADJICHRISTOS ARISTOTELE ,  DONOVAN CONOR ,  LEE SANG-OH

Inventor： CASSIA MARCO ,  HADJICHRISTOS ARISTOTELE ,  DONOVAN CONOR ,  LEE SANG-OH

IPC: H03K17/693 ,  H03K17/0814 ,  H03K17/16

CPC classification number: H03K17/693 ,  Y10T307/696 ,  Y10T307/747

Abstract: A circuit which selects a supply voltage from a plurality of voltage supplies is presented. The circuit includes a first transistor configured to select a first voltage supply, a second transistor configured to select a second voltage supply, a first parasitic current inhibitor coupled the first transistor, the first voltage supply, and the second voltage supply, where the first parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the first transistor, and a second parasitic current inhibitor coupled the second transistor, the first voltage supply, and the second voltage supply, where the second parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the second transistor.

Abstract translation: 提出了从多个电压源中选择电源电压的电路。 该电路包括：第一晶体管，被配置为选择第一电压源;第二晶体管，被配置为选择第二电压源;耦合第一晶体管，第一电压源和第二电压源的第一寄生电流抑制器，其中第一寄生 电流抑制器自动地利用提供最高电压的电压源来防止衬底电流流过第一晶体管的体节点，以及耦合第二晶体管，第一电压源和第二电压源的第二寄生电流抑制器，其中 第二寄生电流抑制器自动利用提供最高电压的电压源来防止衬底电流流过第二晶体管的体节点。

公开(公告)号：WO2008008759A2

公开(公告)日：2008-01-17

申请号：PCT/US2007073129

申请日：2007-07-10

Applicant: QUALCOMM INC ,  ZHUO WEI ,  HADJICHRISTOS ARISTOTELE ,  SAHOTA GURKANWAL KAMAL ,  PENG SOLTI

Inventor： ZHUO WEI ,  HADJICHRISTOS ARISTOTELE ,  SAHOTA GURKANWAL KAMAL ,  PENG SOLTI

IPC: H03D7/16

CPC classification number: H03D7/166 ,  H03H19/008 ,  H03H2007/0192

Abstract: A method according to one embodiment includes using a quadrature set of local oscillator signals having duty cycles of substantially less than fifty percent to perform a mixing operation on a radio-frequency current signal. Other embodiments include using a quadrature set of local oscillator signals having duty cycles of less than twenty-five percent.

Abstract translation: 根据一个实施例的方法包括使用具有基本上小于百分之五十的占空比的本地振荡器信号的正交组来对射频电流信号执行混频操作。 其他实施例包括使用占空比小于百分之二十五的本地振荡器信号的正交集合。