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    DISPOSITIVO DE CIRCUITOS Y UN METODO PARA CONTROLAR UNA OSCILACION DE VOLTAJE.
    11.
    发明专利
    DISPOSITIVO DE CIRCUITOS Y UN METODO PARA CONTROLAR UNA OSCILACION DE VOLTAJE. 未知

    公开(公告)号：MX2009010097A

    公开(公告)日：2009-10-19

    申请号：MX2009010097

    申请日：2008-03-21

    Applicant: QUALCOMM INC

    Inventor： MOHAMMAD BAKER ,  SAINT-LAURENT MARTIN ,  BASSETT PAUL

    IPC: H03K5/08 ,  H03K19/00

    Abstract: Se dan a conocer en particular modalidades ilustrativas, dispositivos de circuitos y métodos para controlar una oscilación de voltaje. El método incluye recibir una señal en una entrada de un dispositivo de circuitos digital que incluye un nodo capacitivo. El método también incluye activar selectivamente un elemento de ajuste de nivel de voltaje para regular una ruta de descarga eléctrica del nodo capacitivo a una tierra eléctrica para evitar la descarga completa del nodo capacitivo. En una modalidad ilustrativa particular, la señal recibida puede ser una señal de reloj.

    CIRCUIT DEVICE AND METHOD OF CONTROLLING A VOLTAGE SWING
    12.
    发明专利
    CIRCUIT DEVICE AND METHOD OF CONTROLLING A VOLTAGE SWING 未知

    公开(公告)号：CA2679364A1

    公开(公告)日：2008-09-25

    申请号：CA2679364

    申请日：2008-03-21

    Applicant: QUALCOMM INC

    Inventor： MOHAMMAD BAKER ,  SAINT-LAURENT MARTIN ,  BASSETT PAUL

    IPC: H03K5/08 ,  H03K19/00

    Abstract: In particular illustrative embodiments, circuit devices and methods of co ntrolling a voltage swing are disclosed. The method includes receiving a sig nal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment elem ent to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock sign al.

    13.
    发明专利
    未知

    公开(公告)号：BRPI0809197A2

    公开(公告)日：2014-09-23

    申请号：BRPI0809197

    申请日：2008-03-21

    Applicant: QUALCOMM INC

    Inventor： MOHAMMAD BAKER ,  SAINT-LAURENT MARTIN ,  BASSETT PAUL

    IPC: H03K5/08 ,  H03K19/00

    Abstract: In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.

    CIRCUIT DEVICE AND METHOD OF CONTROLLING A VOLTAGE SWING
    14.
    发明专利
    CIRCUIT DEVICE AND METHOD OF CONTROLLING A VOLTAGE SWING 未知

    公开(公告)号：CA2679364C

    公开(公告)日：2012-11-06

    申请号：CA2679364

    申请日：2008-03-21

    Applicant: QUALCOMM INC

    Inventor： MOHAMMAD BAKER ,  SAINT-LAURENT MARTIN ,  BASSETT PAUL

    IPC: H03K5/08 ,  H03K19/00

    Abstract: In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.

    LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST
    18.
    发明申请
    LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST 审中-公开
    逻辑设备和方法支持扫描测试

    公开(公告)号：WO2007149808A3

    公开(公告)日：2008-02-07

    申请号：PCT/US2007071450

    申请日：2007-06-18

    Applicant: QUALCOMM INC ,  SAINT-LAURENT MARTIN ,  BASSETT PAUL ,  PATEL PRAYAG

    Inventor： SAINT-LAURENT MARTIN ,  BASSETT PAUL ,  PATEL PRAYAG

    IPC: G01R31/3185

    CPC classification number: G01R31/318552 ,  G01R31/3025 ,  G01R31/318575

    Abstract: A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

    Abstract translation: 逻辑器件包括数据输入，扫描测试输入，时钟解复用器和主锁存器。 时钟解复用器响应时钟输入以选择性地提供第一时钟输出和第二时钟输出。 主锁存器耦合到数据输入和扫描测试输入，并包括一个输出。 主锁存器响应于时钟解复用器的第一时钟输出和时钟多路分解器的第二时钟输出，以选择性地将数据输入或扫描测试输入耦合到输出。

    CLOCK GATING SYSTEM AND METHOD
    19.
    发明申请
    CLOCK GATING SYSTEM AND METHOD 审中-公开
    时钟增益系统和方法

    公开(公告)号：WO2009135226A3

    公开(公告)日：2010-09-10

    申请号：PCT/US2009043913

    申请日：2009-05-14

    Applicant: QUALCOMM INC ,  SAINT-LAURENT MARTIN ,  MOHD BASSAM JAMIL ,  BASSETT PAUL

    Inventor： SAINT-LAURENT MARTIN ,  MOHD BASSAM JAMIL ,  BASSETT PAUL

    IPC: G06F1/04 ,  G06F1/32 ,  G06F17/50 ,  H03K19/017

    CPC classification number: H03K19/0016 ,  G06F1/04

    Abstract: A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

    Abstract translation: 公开了时钟选通系统和方法。 在特定实施例中，系统包括输入逻辑电路，该输入逻辑电路具有至少一个输入端以接收至少一个输入信号并在内部使能节点具有输出。 保持器电路包括响应于门控时钟信号的至少一个开关元件，并且耦合到内部使能节点以选择性地保持内部使能节点处的逻辑电压电平。 该系统还包括响应于输入时钟信号和内部使能节点处的逻辑电压电平的选通元件，以产生门控时钟信号。

    DIGITALLY ASSISTED REGULATION FOR AN INTEGRATED CAPLESS LOW-DROPOUT (LDO) VOLTAGE REGULATOR
    20.
    发明申请
    DIGITALLY ASSISTED REGULATION FOR AN INTEGRATED CAPLESS LOW-DROPOUT (LDO) VOLTAGE REGULATOR 审中-公开
    一体化封装低压差（LDO）电压调节器的数字辅助调节

    公开(公告)号：WO2014150448A2

    公开(公告)日：2014-09-25

    申请号：PCT/US2014023290

    申请日：2014-03-11

    Applicant: QUALCOMM INC

    Inventor： WANG YUHE ,  PEDRALI-NOY MARZIO ,  HUANG XUHAO ,  SAINT-LAURENT MARTIN ,  CHEN XUFENG

    IPC: G05F1/565

    CPC classification number: G05F1/462 ,  G05F1/565 ,  G05F1/575

    Abstract: Techniques are described that embed a digital assisted regulator with an LDO regulator on a chip without requiring a capacitor external to the chip and to regulate a voltage without undershoot. The digital assisted regulator responds to information regarding operation of the LDO regulator and to a signal that provides advance notification of a load change. When the advance notification signal is received, the digital assisted regulator pulls a circuit's supply voltage up to a chip's incoming supply voltage. When the correct operating voltage has been reached and any undershoot problem removed, the digital assisted regulator balances the current it provides with the current provided by the LDO regulator, to allow a quick response time for other load changes. Also, bandwidth of an LDO regulator may be expanded by use of an advance notice signal to increase bias current of an LDO output device to meet an upcoming load change.

    Abstract translation: 描述了将芯片上的LDO调节器嵌入数字辅助调节器的技术，而不需要芯片外部的电容器并且调节电压而不会下冲。 数字辅助稳压器响应关于LDO调节器的操作的信息以及提供负载变化提前通知的信号。 当接收到提前通知信号时，数字辅助调节器将电路的电源电压提升到芯片的输入电源电压。 当达到正确的工作电压并消除任何下冲问题时，数字辅助调节器将其提供的电流与LDO调节器提供的电流平衡，以允许其他负载变化的快速响应时间。 此外，LDO调节器的带宽可以通过使用提前通知信号来扩展，以增加LDO输出设备的偏置电流以满足即将到来的负载变化。

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