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    1.
    发明专利
    未知

    公开(公告)号：BRPI0712764A2

    公开(公告)日：2012-10-02

    申请号：BRPI0712764

    申请日：2007-06-13

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN ,  ZHANG YAN

    IPC: H04L7/02 ,  G06F1/08 ,  H03K5/1252 ,  H04L7/00

    Abstract: Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output. For a limited period of time, a low phase output level is forced. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

    A GLITCH-FREE CLOCK SIGNAL MULTIPLEXER CIRCUIT AND METHOD OFOPERATION
    3.
    发明专利
    A GLITCH-FREE CLOCK SIGNAL MULTIPLEXER CIRCUIT AND METHOD OFOPERATION 未知

    公开(公告)号：CA2653630A1

    公开(公告)日：2007-12-21

    申请号：CA2653630

    申请日：2007-06-13

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN ,  ZHANG YAN

    IPC: H04L7/02 ,  G06F1/08 ,  H03K5/1252 ,  H04L7/00

    Abstract: Techniques for the design and use of a digital signal processor, includin g (but not limited to) for processing transmissions in a communications (e.g ., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a lo w phase output level in the clock output in response to a low phase input le vel in the first clock output. For a limited period of time, a low phase out put level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to provi ding the clock output in response to the second clock input occurs during th e low phase input level in the second clock input signal. Then, the output o f the clock multiplexer follows the phase level of the second clock signal.

    A GLITCH-FREE CLOCK SIGNAL MULTIPLEXER CIRCUIT AND METHOD OF OPERATION
    4.
    发明专利
    A GLITCH-FREE CLOCK SIGNAL MULTIPLEXER CIRCUIT AND METHOD OF OPERATION 未知

    公开(公告)号：CA2653630C

    公开(公告)日：2012-01-03

    申请号：CA2653630

    申请日：2007-06-13

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN ,  ZHANG YAN

    IPC: H04L7/02 ,  G06F1/08 ,  H03K5/1252 ,  H04L7/00

    Abstract: Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output. For a limited period of time, a low phase output level is forced. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

    DISPOSITIVO DE CIRCUITO Y PROCEDIMIENTO PARA MEDIR LA FLUCTUACION DE RELOJ.
    5.
    发明专利
    DISPOSITIVO DE CIRCUITO Y PROCEDIMIENTO PARA MEDIR LA FLUCTUACION DE RELOJ. 未知

    公开(公告)号：ES2365438T3

    公开(公告)日：2011-10-05

    申请号：ES08005117

    申请日：2008-03-19

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN ,  ANDREEV BORIS ,  BASSETT PAUL

    IPC: H03M1/50 ,  G01R29/02 ,  G01R29/26 ,  G01R31/317 ,  H03L7/00

    Abstract: Un procedimiento para detectar una parte deseada de una señal de reloj (102) para determinar una fluctuación de reloj, que comprende: recibir (602) la señal de reloj (102) en una cadena de retardos (206) de un dispositivo de circuito; seleccionar un punto de muestreo dentro de la cadena de retardos (206); muestrear (604) la señal de reloj (102) en el punto de muestreo seleccionado; determinar (606) un valor de la señal de reloj (102) en el punto de muestreo seleccionado en la cadena de retardos (206), en el que el valor de la señal de reloj representa un nivel de la señal de reloj en el punto de muestreo seleccionado; y comparar (608) el valor de la señal de reloj (102) en el punto de muestreo seleccionado para determinar si el valor de la señal de reloj indica la parte deseada; si el valor no indica la parte deseada de la señal de reloj (102), ajustar el punto de muestreo seleccionado hasta que el valor indique la parte deseada.

    6.
    发明专利
    未知

    公开(公告)号：AT477635T

    公开(公告)日：2010-08-15

    申请号：AT07798523

    申请日：2007-06-13

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN ,  ZHANG YAN

    IPC: H04L7/02

    Abstract: Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output. For a limited period of time, a low phase output level is forced. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

    ΚΛΕΙΔΩΜΕΝΟΣ ΒΡΟΧΟΣ ΣΥΧΝΟΤΗΤΑΣ ΒΑΣΙΖΟΜΕΝΟΣ ΣΕ ΤΑΛΑΝΤΩΤΗ
    7.
    发明专利
    ΚΛΕΙΔΩΜΕΝΟΣ ΒΡΟΧΟΣ ΣΥΧΝΟΤΗΤΑΣ ΒΑΣΙΖΟΜΕΝΟΣ ΣΕ ΤΑΛΑΝΤΩΤΗ 未知

    公开(公告)号：CY1116856T1

    公开(公告)日：2017-04-05

    申请号：CY151100865

    申请日：2015-09-29

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN

    IPC: H03L7/00

    Abstract: Μέθοδοςπουπεριλαμβάνειτονκαθορισμόμιαςρύθμισηςελέγχουκαιτηνεπιλεκτικήδιακοπήτηςταλάντωσηςενόςταλαντωτήμετάαπόμιαχρονικήπερίοδο. Οταλαντωτήςείναιρυθμισμένοςώστεναπαραμένεισεενεργήκατάστασημετάτηχρονικήπερίοδο. Ημέθοδοςπεριλαμβάνειεπιπλέοντηνεφαρμογήτηςρύθμισηςελέγχουστονταλαντωτή.

    8.
    发明专利
    未知

    公开(公告)号：BRPI0815032A2

    公开(公告)日：2015-03-10

    申请号：BRPI0815032

    申请日：2008-08-08

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN ,  ANDREEV BORIS ,  BASSETT PAUL

    IPC: H03M1/50

    Abstract: In an embodiment, a method is disclosed that includes receiving a clock signal at a delay chain of a circuit device and determining a value of the clock signal at a selected point within the delay chain. The method also includes adjusting the selected point when the value does not indicate detection of an edge of the clock signal.

    9.
    发明专利
    未知

    公开(公告)号：AT506754T

    公开(公告)日：2011-05-15

    申请号：AT08005117

    申请日：2008-03-19

    Applicant: QUALCOMM INC

    Inventor： SAINT-LAURENT MARTIN ,  ANDREEV BORIS ,  BASSETT PAUL

    IPC: H03M1/50 ,  G01R29/02 ,  G01R29/26 ,  G01R31/317 ,  H03L7/00

    Abstract: In an embodiment, a method is disclosed that includes receiving a clock signal at a delay chain of a circuit device and determining a value of the clock signal at a selected point within the delay chain. The method also includes adjusting the selected point when the value does not indicate detection of an edge of the clock signal.

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