公开(公告)号：JP2012178165A

公开(公告)日：2012-09-13

申请号：JP2012089195

申请日：2012-04-10

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28

CPC classification number: G06F11/362 ,  G06F11/3656

Abstract: PROBLEM TO BE SOLVED: To debug a core processor in association with a multi-threaded digital signal processor.SOLUTION: Writing a stuffing instruction in a debugging process registry and writing a stuffing command in a debugging process command register identify a predetermined thread of the multi-threaded digital signal processor to execute the stuffing instruction. An instruction stuffing process issues a debugging process control resume command during a predetermined execution stage on the predetermined thread, and instructs the core processor to execute the stuffing instruction during the debugging process. Here, the core processor is capable of executing the stuffed instruction in association with the core processor process and the debugging process.

Abstract translation: 要解决的问题：调试与多线程数字信号处理器相关联的核心处理器。 解决方案：在调试过程注册表中写入填充指令并在调试过程命令寄存器中写入填充命令来标识多线程数字信号处理器的预定线程以执行填充指令。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并且指示核心处理器在调试过程中执行填充指令。 这里，核心处理器能够与核心处理器处理和调试过程相关联地执行填充指令。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2013050966A

公开(公告)日：2013-03-14

申请号：JP2012223443

申请日：2012-10-05

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28

CPC classification number: G06F1/3203 ,  G06F11/362 ,  G06F11/3656

Abstract: PROBLEM TO BE SOLVED: To control debugging operation during digital signal processor power transitions.SOLUTION: When a warm boot power-down sequence 220 begins, at point 228, a power collapse interrupt occurs, causing a kernel shutdown handler to operate. In response, the power collapse interrupt is disabled (230). At point 232, the ISDB_CORE_READY register reads 0 and the JTAG read/write returns an invalid status. If an ISDB configuration change is in progress, a core processor causes the power-down sequence to be canceled. If the configuration is not in progress, then the power-down sequence 220 saves the ISDB configuration register contents to memory. A warm boot flag marker is set. Then, the power-down sequence stops all threads and DSP is powered down.

Abstract translation: 要解决的问题：在数字信号处理器电源转换期间控制调试操作。 解决方案：当热引导断电序列220开始时，在点228，发生电源崩溃中断，导致内核关闭处理程序运行。 作为响应，电源崩溃中断被禁用（230）。 在点232，ISDB_CORE_READY寄存器读为0，JTAG读/写返回无效状态。 如果正在进行ISDB配置更改，则核心处理器将导致掉电序列被取消。 如果配置不在进行中，则断电序列220将ISDB配置寄存器内容保存到存储器。 设置热启动标志标记。 然后，掉电序列停止所有线程，DSP断电。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013254508A

公开(公告)日：2013-12-19

申请号：JP2013151110

申请日：2013-07-19

Applicant: QUALCOMM INC

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28

Abstract: PROBLEM TO BE SOLVED: To capture detailed information on an execution flow of a DSP in real time in a non-intrusive manner.SOLUTION: An ETM 232 monitors a DSP pipeline. Using this information, the ETM performs filtering/triggering and compression/packetization. The filtering and triggering operations are programmed by a user through a JTAG interface 84. DSP execution information is received by a compression/packetization unit 236, sent out of the ETM through a trace port, and fed into an off-chip or on-chip trace repository 240. A decompressor component 246 is a software component running on an ISDB 82, and takes a packet stream from the trace repository and, along with a program image, reconstructs an execution flow of the DSP, giving the user detailed visibility of the DSP pipeline.

公开(公告)号：JP2013058207A

公开(公告)日：2013-03-28

申请号：JP2012209762

申请日：2012-09-24

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

Abstract: PROBLEM TO BE SOLVED: To provide non-intrusive debugging to real-time behavior in a multi-threaded DSP.SOLUTION: An ISDB is enabled (132) for DSP operation. If a hardware breakpoint 134, a software breakpoint 136, an ETM breakpoint 140, a JTAG breakpoint 142, or an external breakpoint 144 exists, the process proceeds to debugging operation 138. ISTEP debugging 150 is performed if the ISTEP debugging is effective. Instruction stuffing operation 154 is performed if the instruction stuffing operation is effective. If a core DSP reset instruction has been generated by the debugging operation, a core DSP digital signal processor is reset (156).

Abstract translation: 要解决的问题：为多线程DSP中的实时行为提供非侵入式调试。 解决方案：使能ISDB（132）进行DSP操作。 如果存在硬件断点134，软件断点136，ETM断点140，JTAG断点142或外部断点144，则处理进行到调试操作138.如果ISTEP调试有效，则执行ISTEP调试150。 如果指示填充操作有效，则执行指令填充操作154。 如果通过调试操作生成了核心DSP复位指令，则核心DSP数字信号处理器被复位（156）。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：ES2259322T3

公开(公告)日：2006-10-01

申请号：ES01914457

申请日：2001-02-23

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  CHEN XUFENG ,  HSU DE D

IPC: G06F7/00 ,  G06F7/544 ,  G06F17/10

Abstract: Un circuito electrónico (200) para realizar selectivamente varias operaciones independientes de multiplicación acumulación en un solo ciclo de reloj o una operación de adición de dos productos en un solo ciclo de reloj, el circuito electrónico (200) comprende: un archivo de registro (202) que tiene una primera y una segunda entrada (PI1, PI2) y en primera instancia a través de seis salidas (PO1 a PO6); un primer multiplicador (206) que recibe la segunda y la tercera salida (PO2, PO3) del archivo de registro (202) y que tiene una salida; y un segundo multiplicador (208) que recibe la cuarta y la quinta salida (PO4, PO5) del archivo de registro (202) y que tiene una salida; un primer conmutador (204) que recibe la primera salida (PO1) del archivo de registro (202); un segundo conmutador (210) que recibe la salida del primer multiplicador (206) y que tiene una salida; un tercer conmutador (212) que recibe la salida del segundo multiplicador (208) y que tiene una salida; un multiplexor de redondeo (214) que recibe la salida del primer conmutador (204) y que tiene una salida; una primera sumadora (216) que recibe, en una primera entrada, la salida del segundo conmutador (210) y que tiene una salida; un multiplexor (218) configurado para proporcionar, de acuerdo con la operación seleccionada, un cero o la salida del tercer conmutador (212) y que aplica una salida a una segunda entrada de la primera sumadora (216); una segunda sumadora (220) que recibe las salidas del multiplexor de redondeo (214) y la primera sumadora (216), y que tiene una salida que se realimenta a la primera entrada del archivo de registro (202); y una tercera sumadora (222) que recibe las salidas del tercer conmutador (212) y la sexta salida del registro (PO6), y que tiene una salida que se realimenta a la segunda entrada (PI2) del archivo de registro (202).

公开(公告)号：CA2558367A1

公开(公告)日：2005-09-29

申请号：CA2558367

申请日：2005-03-02

Applicant: QUALCOMM INC

Inventor： CHEN XUFENG ,  SIH GILBERT C ,  LEE WAY-SHING ,  HSU DE D

IPC: G06F7/48 ,  G06F7/57 ,  G06F9/30

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

公开(公告)号：HUE038872T2

公开(公告)日：2018-12-28

申请号：HUE08005116

申请日：2008-03-19

Applicant: QUALCOMM INC

Inventor： GIANNINI LOUIS ACHILLE ,  ANDERSON WILLIAM C ,  CHEN XUFENG

IPC: G06F11/36

公开(公告)号：AU3984401A

公开(公告)日：2001-09-03

申请号：AU3984401

申请日：2001-02-23

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  CHEN XUFENG ,  HSU DE D

IPC: G06F7/00 ,  G06F7/544 ,  G06F17/10

Abstract: Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.

公开(公告)号：CA2400647C

公开(公告)日：2010-06-29

申请号：CA2400647

申请日：2001-02-23

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  CHEN XUFENG ,  HSU DE D

IPC: G06F7/00 ,  G06F7/544 ,  G06F17/10

Abstract: Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C) + (D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.

公开(公告)号：DE60116742D1

公开(公告)日：2006-04-06

申请号：DE60116742

申请日：2001-02-23

Applicant: QUALCOMM INC

Inventor： SIH C ,  CHEN XUFENG ,  HSU D

IPC: G06F7/00 ,  G06F7/544 ,  G06F17/10

Abstract: Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.