公开(公告)号：WO2016137733A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/016996

申请日：2016-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik Daniel ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  BERDY, David Francis ,  ZUO, Chengjie ,  KIM, Jonghae ,  NOWAK, Matthew Michael

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/00 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

Abstract translation: 接地屏蔽通过具有导电表面的导体屏蔽来实现，导电表面立即围绕多芯片模块或器件（例如具有倒装芯片（FC）凸块的多芯片模块或器件）中的单个芯片。 多芯片模块或设备内的单个芯片之间的模块间屏蔽通过由紧邻每个芯片的导体屏蔽表面提供的电磁或射频信号（RF）隔离来实现。 导体屏蔽件直接连接到基板或插入件的一个或多个接地导体部分，以确保可靠的接地。

公开(公告)号：WO2016048629A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/048597

申请日：2015-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik Daniel ,  LAN, Je-Hsiung Jeffrey ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  KIM, Jonghae ,  BERDY, David Francis

IPC: H01L23/00

CPC classification number: H05K1/0271 ,  C23F1/02 ,  H01L21/768 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0154 ,  H05K2201/0195 ,  H01L2924/00

Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.

Abstract translation: 器件包括在衬底（例如，半导体管芯或其他集成电路）的至少两个应力结构域之间的应力消除区域。 应力消除区域包括导电结构，电耦合应力区域的电路，导电结构设置在该应力区域之间。

公开(公告)号：WO2015126640A1

公开(公告)日：2015-08-27

申请号：PCT/US2015/014895

申请日：2015-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： VELEZ, Mario Francisco ,  KIM, Daeik Daniel ,  SONG, Young Kyu ,  ZHANG, Xiaonan ,  KIM, Jonghae ,  YUN, Changhan Hobie ,  ZUO, Chengjie

IPC: H01L23/13 ,  H01L23/498 ,  H01F17/00 ,  H01L49/02

CPC classification number: H05K1/182 ,  H01F17/0006 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/10 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/10242 ,  H05K2201/10984 ,  Y10T29/49165

Abstract: A low-profile passive-on-package is provided that includes a plurality of recesses that receive corresponding interconnects. Because of the receipt of the interconnects in the recesses, the passive-on-package has a height that is less than a sum of a thickness for the substrate and an interconnect height or diameter.

Abstract translation: 提供了一种低调无源封装，其包括接收相应互连的多个凹槽。 由于在凹槽中接收到互连，所以被动封装的高度小于衬底的厚度和互连高度或直径的总和。

公开(公告)号：WO2015120375A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/014995

申请日：2015-02-09

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  ZUO, Chengjie ,  KIM, Jonghae ,  VELEZ, Mario Francisco ,  KIDWELL, JR., Donald William ,  LASITER, Jon Bradley ,  LAI, Kwan-Yu ,  KIM, Jitae ,  SHENOY, Ravindra Vaman

IPC: H01L49/02 ,  H01G4/33 ,  H01G4/012 ,  H01L21/48 ,  H01L27/12

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract translation: 提供的空间效率电容器具有比传统设计更高的品质因数，并且改善了从直通玻璃通孔（TGV）到电介质的电能的耦合。 例如，提供了具有非矩形横截面的TGV，其中TGV的一端耦合到第一金属板。 在第一金属板上形成电介质材料。 第二金属板以与第一金属板的至少一部分重叠以形成电介质材料的至少一个重叠区域的方式形成在电介质材料上。 重叠区域的周边的至少一部分是非平面的。 重叠区域可以形成为环形的多个部分中的大致四分之一环形的闭环形状和/或大致一半的环形形状。

公开(公告)号：WO2014193525A1

公开(公告)日：2014-12-04

申请号：PCT/US2014/031779

申请日：2014-03-25

Applicant: QUALCOMM INCORPORATED

Inventor： ZUO, Chengjie ,  KIM, Jonghae ,  YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  LAN, Je-Hsiung ,  MIKULKA, Robert Paul ,  NOWAK, Matthew Michael

IPC: H03H7/01

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 直通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。

公开(公告)号：WO2014182556A1

公开(公告)日：2014-11-13

申请号：PCT/US2014/036524

申请日：2014-05-02

Applicant: QUALCOMM INCORPORATED

Inventor： ZUO, Chengjie ,  KIM, Daeik, D. ,  LAN, Je-Hsiung ,  KIM, Jonghae ,  VELEZ, Mario, Francisco ,  YUN, Changhan ,  BERDY, David, F. ,  MIKULKA, Robert, P. ,  NOWAK, Matthew, M. ,  ZHANG, Xiangdong ,  SEE, Puay, H.

IPC: H03H7/46

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

公开(公告)号：WO2014150747A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024118

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： LAN, Je-Hsiung ,  ZUO, Chengjie ,  YUN, Changhan ,  BERDY, David F. ,  KIM, Daeik D. ,  MIKULKA, Robert P. ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC: H01L23/498 ,  H01F17/00

CPC classification number: H01L28/40 ,  G06F17/5068 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L27/016 ,  H01L27/12 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

Abstract translation: 在特定实施例中，器件包括衬底，至少部分延伸穿过衬底的通孔和电容器。 电容器的电介质位于电容器的通孔和板之间，并且电容器的板在衬底外部和器件内部。

公开(公告)号：WO2014081983A1

公开(公告)日：2014-05-30

申请号：PCT/US2013/071349

申请日：2013-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： LO, Chi Shun ,  LAN, Je- Hsiung ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC: H01L49/02 ,  H01F19/04 ,  H01L23/522 ,  H01L23/64 ,  H01F19/08 ,  H01F27/28

CPC classification number: H01L28/10 ,  H01F19/04 ,  H01F21/00 ,  H01F2019/085 ,  H01F2027/2809 ,  H01L21/00 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

Abstract: Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings (702) positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port (706) and a second port (708). The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings (704) positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port (710), a fourth port (712) and a fifth port (714). The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.

Abstract translation: 几种新颖特征涉及形成在具有多层的半导体管芯内的混合变压器。 混合变压器包括定位在模具的第一层上的第一组绕组（702）。 第一层位于模具的基底之上。 第一组绕组包括第一端口（706）和第二端口（708）。 第一组绕组被布置成作为第一电感器工作。 混合变压器包括位于模具的第二层上的第二组绕组（704）。 第二层位于衬底上方。 第二组绕组包括第三端口（710），第四端口（712）和第五端口（714）。 第二组绕组被布置成用作第二电感器和第三电感器。 第一组绕组和第二组绕组被布置成作为垂直耦合混合变压器工作。

公开(公告)号：WO2011025897A1

公开(公告)日：2011-03-03

申请号：PCT/US2010/046862

申请日：2010-08-26

Applicant: QUALCOMM Incorporated ,  KIM, Jonghae ,  WANG, Feng ,  NOWAK, Matthew

Inventor： KIM, Jonghae ,  WANG, Feng ,  NOWAK, Matthew

IPC: H01L23/64 ,  H01L23/66 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01L21/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatuses for transformer signal coupling for flip-chip circuit assemblies are presented. A device for coupling dies in flip-chip circuit assembly may include a first die associated with a first fabrication process and a first inductor physically coupled to the first die, where the first inductor receives an RF input signal. The device may further include a second die associated with a second fabrication process, and a second inductor physically coupled to the second die, where the second inductor is positioned so the first inductor can inductively couple the RF signal in the second inductor. A method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer.

Abstract translation: 提出了用于倒装芯片电路组件的变压器信号耦合的方法和装置。 用于在倒装芯片电路组件中耦合管芯的装置可以包括与第一制造工艺相关联的第一管芯和物理耦合到第一管芯的第一电感器，其中第一电感器接收RF输入信号。 该器件还可以包括与第二制造工艺相关联的第二管芯，以及物理耦合到第二管芯的第二电感器，其中第二电感器被定位成使得第一电感器可感应地耦合第二电感器中的RF信号。 用于提供管芯之间的感应耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及组装每个管芯，使得第一和第二电感器被配置为 变压器

公开(公告)号：WO2023064661A1

公开(公告)日：2023-04-20

申请号：PCT/US2022/076503

申请日：2022-09-15

Applicant: QUALCOMM INCORPORATED

Inventor： LIU, Kai ,  LAN, Je-Hsiung ,  KIM, Jonghae

IPC: H03H9/05 ,  H03H9/10 ,  H03H3/02 ,  H03H3/08 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed is a radio frequency, RF, filter (500-1, 500-2) that vertically integrates an acoustic die (510, 514) with 2D or 3D inductors formed in one or more layers (520,530,540) above the acoustic die. The acoustic die is over-molded so that the acoustic dome, important for maintaining acoustic integrity, may be protected. 2D inductors may be formed in RDL layers (520,540,545,555) on the over-mold (515). 3D inductors may be formed with through-mold vias (530) in a second mold (535) formed above the over-mold (515). Fabrication of through-mold vias may be by mold-first or copper-pillar-first method.