公开(公告)号：WO1992008161A1

公开(公告)日：1992-05-14

申请号：PCT/US1991007551

申请日：1991-10-09

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  BULLINGTON, Jeff, Allen

IPC: G02F03/00

CPC classification number: G02F1/293 ,  G02F3/00

Abstract: A light activated AND gate (10) is disclosed which generates a light signal at a first output port (14) in response to the simultaneous presence of light signals at an input port (12) and a control port (18). With a light signal present at the control port (18), a light beam at the input port (12) is reflected from an interface between two regions (13, 15) having different indices of refraction, and the reflected light beam then exits through a first output port (16). In the absence of a light signal at the control port (18), the two regions (13, 15) of the switching device (10) have the same index of refraction, and the light beam at the input port (12) passes through both regions (13, 15) and exits through a second output port (14).

公开(公告)号：WO1999023661A1

公开(公告)日：1999-05-14

申请号：PCT/US1997020440

申请日：1997-10-31

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  WOMACK, Richard, H. ,  EVANS, Joseph, Tate, Jr.

IPC: G11C11/22

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L29/78391

Abstract: A memory (500) based on a ferroelectric FET, the ferroelectric FET includes a gate electrode (14), a layer of ferroelectric material (16), layer of semiconducting material (18), a source electrode (21) and a drain electrode (22). The layer of ferroelectric material (16) is sandwiched between the gate electrode (14) and the layer of semiconducting material (18), the source and drain electrodes being in contact with the layer of semiconducting material and spaced apart from one another. The memory (500) includes a circuit for setting the ferroelectric FET to one of two states. The first state is set by applying a first voltage to the source and drain electrodes and a second voltage to the gate electrode. The second state is set by applying a third voltage to the gate and drain electrodes and fourth voltage to the source electrode. This arrangement reduces the number of pass transistors needed per ferroelectric FET to one plus a simple pulsing circuit that must be included with each word of memory.

Abstract translation: 一种基于铁电FET的存储器（500），所述强电介质FET包括栅电极（14），铁电体层（16），半导体材料层（18），源电极（21）和漏电极 22）。 铁电材料层（16）夹在栅电极（14）和半导体材料层（18）之间，源电极和漏电极与半导体材料层接触并彼此间隔开。 存储器（500）包括用于将铁电FET设置为两种状态之一的电路。 通过向源极和漏极施加第一电压并将第二电压施加到栅电极来设定第一状态。 通过向栅极和漏极施加第三电压并将第四电压施加到源电极来设定第二状态。 这种布置将每个铁电FET所需的通过晶体管的数量减少到一个加上每个单词存储器必须包含的简单脉冲电路。

公开(公告)号：WO1998033184A1

公开(公告)日：1998-07-30

申请号：PCT/US1997024282

申请日：1997-12-31

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  WOMACK, Richard

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A memory (500) for storing a plurality of words of data. Each of the words includes N data bits, where N is an integer greater than 1. The memory (500) includes a plurality of storage cells, each of the word storage cells having N + 1 single bit memory cells (512, 513, 514, 517). The single bit memory cells (512, 513, 514, 517) are numbered from 1 to N + 1. Each of the single bit memory cells (512, 513, 514, 517) connects a conductor in a word bus common to all of the memory cells in that word to a bit line that is connected in common to all of the single bit memory cells (512, 513, 514, 517) having the same number. The word bus also includes a conductor for transmitting a signal indicating that this connection is to be made. Each of the single bit memory cells (512, 513, 514) having a number between 1 and N stores one of the N data bits. The memory (500) also includes N sense amplifiers (550, 560, 570), one of the sense amplifiers (550, 560, 570) being connected to each of the bit lines to which the bits numbered 1 to N are connected. Each of the sense amplifiers (550, 560, 570) compares a signal on the bit line (551-553) connected thereto to a signal on the bit line (557) connected to the single bit memory cells (517) numbered (N + 1). When data is written into the data bits of the word, a predetermined value is preferably written into the single bit memory cell (517) number N + 1. Embodiments of the present invention based on ferroelectric FET memory cells (10) or ferroelectric capacitor-based memory cells (100) are preferred.

Abstract translation: 一种用于存储多个数据字的存储器（500）。 每个字包括N个数据位，其中N是大于1的整数。存储器（500）包括多个存储单元，每个字存储单元具有N + 1个单位存储器单元（512,513,514 ，517）。 单位存储器单元（512,513,514,571）从1到N + 1编号。单个位存储单元（512,513,514,571）中的每一个将公用的字总线中的导体连接到 该字中的存储单元与一个与所有具有相同数目的单位存储单元（512,513,514,571）共同连接的位线。 字母线还包括用于发送指示要进行该连接的信号的导体。 具有1和N之间的数字的单个位存储器单元（512,513,514）中的每一个存储N个数据位之一。 存储器（500）还包括N个读出放大器（550,560,570），读出放大器（550,560,570）中的一个连接到连接有编号为1到N的位的每个位线。 每个读出放大器（550,560,570）将连接到其上的位线（551-553）上的信号与连接到编号为（N + 1）的单位存储单元（517）的位线（557）上的信号进行比较， 1）。 当数据被写入字的数据位时，优选地将预定值写入到数字N + 1的单位存储单元（517）中。本发明的实施例基于铁电FET存储单元（10）或铁电电容器 - （100）。

公开(公告)号：WO1996028844A1

公开(公告)日：1996-09-19

申请号：PCT/US1996003230

申请日：1996-03-08

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  BOYER, Lenard

IPC: H01L21/44

CPC classification number: H01L28/60 ,  H01L28/55 ,  Y10S148/014 ,  Y10S148/10

Abstract: A method for making an improved LSCO stack in the generation of small platinum features (46) on the surface of a substrate (32) by sputtering of the LSCO material (54) and utilizing a photoresist mask to pattern the LSCO (54) in accordance with the platinum features (46). The problems and expense associated with high-temperature deposition of LSCO on platinum and the etching thereof are overcome by sputtering the LSCO at room temperature.

Abstract translation: 一种通过溅射LSCO材料（54）并利用光致抗蚀剂掩模在基板（32）的表面上产生小的铂特征（46）来制造改进的LSCO堆叠的方法，以按照 与铂金功能（46）。 通过在室温下溅射LSCO来克服与LSCO在铂上的高温沉积相关的问题和费用及其蚀刻。

公开(公告)号：WO1996015556A1

公开(公告)日：1996-05-23

申请号：PCT/US1995014875

申请日：1995-11-15

Applicant: RADIANT TECHNOLOGIES, INC. ,  JOSEPH, Tate, Evans, Jr.

Inventor： RADIANT TECHNOLOGIES, INC.

IPC: H01L27/108

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L28/40

Abstract: The invention is applicable to integrated circuit having ferroelectric layers that are switched between two states during the operation of the integrated circuit. In the present invention (10), a capacitor (19) has a ferroelectric layer (22) constructed from a material having a Curie point below 400 DEG C. In the typical integrated circuit fabrication process, the final step in the process before packaging involves annealing the circuit at a temperature above the Curie point of the ferroelectric layer used in an integrated circuit according to the present invention. Hence, any accumulated asymmetric charge distribution in the ferroelectric layer resulting from the processing of the integrated circuit after the deposition of the ferroelectric layer is eliminated. If the normal fabrication process does not involve a final annealing step at a temperature above the Curie point of the ferroelectric layer, a final annealing step in which the ferroelectric is annealed at a temperature above its Curie point is used.

Abstract translation: 本发明可应用于在集成电路的操作期间具有在两种状态之间切换的铁电层的集成电路。 在本发明（10）中，电容器（19）具有由居里点低于400℃的材料构成的铁电体层（22）。在典型的集成电路制造工艺中，封装前的工艺的最后步骤包括 在根据本发明的集成电路中使用的铁电层的居里点以上的温度下退火。 因此，消除了在堆积铁电层之后由集成电路的处理产生的铁电体层中的任何累积的非对称电荷分布。 如果正常的制造工艺在高于铁电体的居里点的温度下不涉及最终退火步骤，则使用在高于其居里点的温度下退火强电介质的最终退火步骤。

公开(公告)号：WO1993016811A1

公开(公告)日：1993-09-02

申请号：PCT/US1993000259

申请日：1993-01-13

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  BULLINGTON, Jeff ,  ELLIS, Robert, V. ,  WALKER, Richard, T.

IPC: B05D03/06

CPC classification number: C23C16/48 ,  C23C16/409 ,  C23C16/452

Abstract: A method for coating the surface of a substrate with a thin film of ferroelectric material. A flow of a metalorganic vapor such as tetraethyl lead, zirconium t-butoxide, and titanium isopropoxide is directed towards a silicon substrate. Also, a flow of ionized particles is generated by subjecting a gas to an rf electromagnetic field. The afterglow of excited state species particles intersects the path of the flow of metalorganic vapor at a location displaced from the surface of the substrate producing a flow of activated metalorganic vapor which then deposits on the heated substrate. The figure illustrates a plasma enhanced chemical vapor deposition reactor which consists of a plasma generator (10) where the excited species is generated, a precursor activation chamber (20), the deposition region where the heated substrate (32) is located, and an exhaust system (40).

Abstract translation: 一种用铁电材料薄膜涂覆基板的表面的方法。 诸如四乙基铅，叔丁醇锆和异丙醇钛的金属有机蒸气的流动指向硅衬底。 此外，通过使气体经受射频电磁场而产生电离粒子的流动。 激发态物质颗粒的余辉与位于离开衬底表面的位置处的金属有机蒸汽流的路径相交，产生活化的金属有机蒸气，然后沉积在加热的衬底上。 该图示出了等离子体增强化学气相沉积反应器，其由产生激发物质的等离子体发生器（10），前体活化室（20），加热的基底（32）所在的沉积区域和排气 系统（40）。

公开(公告)号：WO1991018305A1

公开(公告)日：1991-11-28

申请号：PCT/US1991003085

申请日：1991-05-06

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  BULLINGTON, Jeff, Allen

IPC: G02B05/23

CPC classification number: G02B6/3522 ,  G02B6/355 ,  G02B6/3596 ,  G02F1/0126 ,  G02F1/293 ,  G02F1/3137

Abstract: A light activated switching device (10) is disclosed in which the receipt of a light signal is used to switch a light beam between two output ports (14) and (16). The input light beam is reflected from an interface between two regions having different indices of refraction when the light signal is present. The reflected light beam then exits through the first output port (16). In the absence of the light signal, the two regions have the same index of refraction, and the light beam passes through both regions and exits through the second output port (14).