公开(公告)号：DK163685D0

公开(公告)日：1985-04-11

申请号：DK163685

申请日：1985-04-11

Applicant: RCA CORP

Inventor： FLING RUSSEL THOMAS ,  WILLIS DONALD HENRY ,  MCNEELY DAVID LOWELL

IPC: H04N5/202 ,  H03G3/00 ,  H03G3/20 ,  H04N9/68 ,  H04N

Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.

公开(公告)号：ES2000378A6

公开(公告)日：1988-02-16

申请号：ES8600549

申请日：1986-07-24

Applicant: RCA CORP

Inventor： FLING RUSSEL THOMAS

IPC: H04N7/01 ,  H04N5/14 ,  H04N5/44 ,  H04N5/05 ,  H04N5/46

Abstract: EL SISTEMA CORRIGE SEÑALES DE VIDEO RETARDANDO (95,96,98) LA SEÑAL DE SALIDA DE LA MEMORIA (50) EN FUNCION DE DISTORSIONES DE RELOJ DE LEER Y ESCRIBIR, MIDIENDOSE LA DISTORSION DE ESCRIBIR PARA CADA CICLO DE LEER-ESCRIBIR DE LA MEMORIA. LA DISTORSION DE LEER (ENGANCHE 66) DEL PRIMER CICLO DE LEER CORRESPONDE A LA DISTORSION DE ESCRIBIR (ENGANCHE 64) AL COMIENZO DE ESE CICLO. LA DISTORSION DE LEER DEL SEGUNDO CICLO DE LEER SE OBTIENE AÑADIENDO A LA DISTORSION DE LEER UN SEMIPERIODO DE LINEA DE LA SEÑAL DE ENTRADA DE VIDEO Y TOMANDO SU PARTE FRACCIONARIA.SE DETECTA (68) LA PARTE ENTERA DE LA SUMA INICIANDO EL COMIENZO DEL SEGUNDO CICLO DE LEER. LA DIFERENCIA (86) ENTRE LA SEÑAL DE DISTORSION DE LEER (64) Y EL DOBLE (84) DE LA SEÑAL DE DISTORSION DE ESCRIBIR (66) DETERMINA EL RETARDO DE LA SEÑAL DE VIDEO.

公开(公告)号：IT1175497B

公开(公告)日：1987-07-01

申请号：IT2092584

申请日：1984-05-15

Applicant: RCA CORP

Inventor： FLING RUSSEL THOMAS ,  SAIPRASAD VASUDEV NAIMPALLY

IPC: G06F7/38 ,  G06F7/48 ,  G06F7/499 ,  H04N7/26 ,  H04N9/00 ,  H04N

Abstract: Symmetrical truncation of two's complement binary numbers is performed by simply discarding the LSB's of positive values and by adding "one" to the truncated negative value when any one of the discarded LSB's is a logical "one" value. Apparatus to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.

公开(公告)号：DK134886D0

公开(公告)日：1986-03-24

申请号：DK134886

申请日：1986-03-24

Applicant: RCA CORP

Inventor： FLING RUSSEL THOMAS

IPC: H04N5/21 ,  G06F7/38 ,  G06F7/48 ,  G06F17/10 ,  H03H17/04 ,  H04N

Abstract: A scaling circuit for scaling PCM signals by factors less than one includes a bit-shift and truncating circuit (61). Roundoff error compensating circuitry adds (60) an offset value - (38)to the samples (15) to be scaled by the bit-shift circuitry to compensate for errors produced by truncation without rounding. The offset values may be dithered to increase the apparent resolution of the system.

公开(公告)号：FR2563069A1

公开(公告)日：1985-10-18

申请号：FR8505474

申请日：1985-04-11

Applicant: RCA CORP

Inventor： FLING RUSSEL THOMAS

IPC: H04N5/208 ,  H04N5/14 ,  H04N9/78 ,  G06F15/68

Abstract: In processing comb filtered video signals it is desirable to separate lower frequency vertical detail signal from comb filtered chrominance and recombine it with the comb filtered luminance signal. System response is enhanced if the vertical detail is non-linear processed before it is recombined with luminance. To core, peak and pare digital vertical detail signal, the signal is passed through an absolute value circuit and then applied to a first signal combiner wherein a first reference value is subtracted from the magnitudes of the input signals. The differences are applied to a polarity discriminator which passes difference values of only one polarity. The one polarity differences are scaled and applied to one input port of a signal combining circuit. The one polarity differences are also applied to a third signal combining circuit wherein a second reference value is subtracted from the one polarity differences to produce a double difference value. The double difference value is applied to a second polarity discriminator which couples one polarity double difference values to a second input port of the second signal combining circuit, the output of which exhibits a piecewise linear, non-linear transfer characteristic.