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公开(公告)号：FR2585913A1
公开(公告)日：1987-02-06
申请号：FR8611064
申请日：1986-07-30
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , FLING RUSSEL THOMAS , CHRISTOPHER TODD J
Abstract: In memory-based video signal processing systems such as frame recursive filters, for example, system performance is dependent upon critical timing relationships between incoming signals and delayed signals produced from the memory. Video signal from various sources, e.g. VTR's, tend to have jittering time bases that generally have prevented the use of such memory-based processing systems. The jittering signals may be standardized, in sampled data format, by effecting adaptive signal delays responsive to a measure of the relative phase of the sampling clock with respect to horizontal synchronizing pulses. The phase measure is used to control an interpolator which combines successive samples in proportions to develop sample values that should have occurred at the sample times had the signal not been jittering.
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公开(公告)号：FR2563068A1
公开(公告)日：1985-10-18
申请号：FR8505473
申请日：1985-04-11
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS , WILLIS DONALD HENRY , MCNEELY DAVID LOWELL
Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.
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公开(公告)号：DK134886A
公开(公告)日：1986-09-26
申请号：DK134886
申请日：1986-03-24
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS
Abstract: A scaling circuit for scaling PCM signals by factors less than one includes a bit-shift and truncating circuit (61). Roundoff error compensating circuitry adds (60) an offset value - (38)to the samples (15) to be scaled by the bit-shift circuitry to compensate for errors produced by truncation without rounding. The offset values may be dithered to increase the apparent resolution of the system.
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公开(公告)号：DK134986D0
公开(公告)日：1986-03-24
申请号：DK134986
申请日：1986-03-24
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS , CHRISTOPHER TODD J
Abstract: A pix-in-pix display includes a filtering system for processing the video signals which produce the reduced-size image. The filtering system includes an anti-aliasing filter - (210) which reduces the amplitude of the components of the video signals which may cause aliasing distortion when the image is subsampled. However, the filter passes substantial amounts of these components. The filtered video signal is subsampled (212) and applied to a peaking filter (220) which amplifies the band of frequencies containing the aliasing components relative to lower frequency bands to improve the appearance of detailed portions of the reproduced image.
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公开(公告)号：FR2585913B1
公开(公告)日：1992-01-24
申请号：FR8611064
申请日：1986-07-30
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , FLING RUSSEL THOMAS , CHRISTOPHER TODD J
Abstract: In memory-based video signal processing systems such as frame recursive filters, for example, system performance is dependent upon critical timing relationships between incoming signals and delayed signals produced from the memory. Video signal from various sources, e.g. VTR's, tend to have jittering time bases that generally have prevented the use of such memory-based processing systems. The jittering signals may be standardized, in sampled data format, by effecting adaptive signal delays responsive to a measure of the relative phase of the sampling clock with respect to horizontal synchronizing pulses. The phase measure is used to control an interpolator which combines successive samples in proportions to develop sample values that should have occurred at the sample times had the signal not been jittering.
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Patent Agency Ranking
公开(公告)号：FR2563068B1
公开(公告)日：1988-11-10
申请号：FR8505473
申请日：1985-04-11
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS , WILLIS DONALD HENRY , MCNEELY DAVID LOWELL
Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.
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公开(公告)号：FR2585916A1
公开(公告)日：1987-02-06
申请号：FR8611063
申请日：1986-07-30
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , FLING RUSSEL THOMAS , CHRISTOPHER TODD J
Abstract: A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce visual artifacts in the displayed image due to clock skew relative to sync when non-standard video signals are processed. The skew errors are corrected by circuitry which measures the skew of the read and write clocks and delays the video signal as a function of a difference between the clock skew measurements.
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公开(公告)号：FR2563069B1
公开(公告)日：1989-02-03
申请号：FR8505474
申请日：1985-04-11
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS
Abstract: In processing comb filtered video signals it is desirable to separate lower frequency vertical detail signal from comb filtered chrominance and recombine it with the comb filtered luminance signal. System response is enhanced if the vertical detail is non-linear processed before it is recombined with luminance. To core, peak and pare digital vertical detail signal, the signal is passed through an absolute value circuit and then applied to a first signal combiner wherein a first reference value is subtracted from the magnitudes of the input signals. The differences are applied to a polarity discriminator which passes difference values of only one polarity. The one polarity differences are scaled and applied to one input port of a signal combining circuit. The one polarity differences are also applied to a third signal combining circuit wherein a second reference value is subtracted from the one polarity differences to produce a double difference value. The double difference value is applied to a second polarity discriminator which couples one polarity double difference values to a second input port of the second signal combining circuit, the output of which exhibits a piecewise linear, non-linear transfer characteristic.
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公开(公告)号：DK134986A
公开(公告)日：1986-09-26
申请号：DK134986
申请日：1986-03-24
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS , CHRISTOPHER TODD J
Abstract: A pix-in-pix display includes a filtering system for processing the video signals which produce the reduced-size image. The filtering system includes an anti-aliasing filter - (210) which reduces the amplitude of the components of the video signals which may cause aliasing distortion when the image is subsampled. However, the filter passes substantial amounts of these components. The filtered video signal is subsampled (212) and applied to a peaking filter (220) which amplifies the band of frequencies containing the aliasing components relative to lower frequency bands to improve the appearance of detailed portions of the reproduced image.
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公开(公告)号：DK163685A
公开(公告)日：1985-10-13
申请号：DK163685
申请日：1985-04-11
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS , WILLIS DONALD HENRY , MCNEELY DAVID LOWELL
Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.
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