Abstract:
A first biasing transistor has at least a portion of its base current supplied by the emitter current of a second biasing transistor. The collector current of the first transistor is larger than the collector current of the second transistor by a factor proportional to the hfe current gain characteristic of the first transistor. The collector current of the first transistor is used to establish the quiescent collector-to-emitter current flow of an amplifier transistor having an hfe which matches that of the first biasing transistor. The collector current of the second transistor is used to establish the level quiescent base current supplied to the amplifier for supporting the latter quiescent collector-to-emitter current flow. This avoids quiescent base current drain from the circuitry providing input signal to the amplifier transistor.
Abstract:
Input signals are coupled in common to the emitter electrodes of a pair of transistors arranged in a differential amplifier configuration, and are synchronously detected by switching signals coupled to the respective transistor base electrodes. The coupling to the emitter electrodes is through a transistor arranged in a common-base amplifier construction, with the signals to be demodulated being applied to the amplifier transistor emitter electrode via an included stabilizing resistor.
Abstract:
A sample-and-hold circuit employs first and second transistors of the same conductivity type, having serially coupled collectorto-emitter current paths and including a feedback path coupling the collector of the first transistor to the base of the second transistor to provide a high-input impedance and a relatively low-output impedance circuit suitable for rapid updating of a hold capacitor. The circuit samples an applied signal when the first and second transistors are keyed into conduction by keying circuit means, and holds when these transistors are biased out of conduction. The circuit is particularly suited for application as a phase comparator.
Abstract:
Average detection apparatus employing pulse-stretching techniques for increasing the energy content and compressing the dynamic pulse width range of a pulse train including randomly occurring, short duration, widely spaced pulses. The pulse train and a train of reference pulses are supplied to a bistable storage element to set and reset the element, respectively, to first and second output states. An average detector is coupled to the output of the storage element.
Abstract:
An electrical circuit especially suited for fabrication using integrated circuit techniques including a common emitter transistor amplifier connected in cascade relation with a common collector transistor amplifier and interconnected with a pair of resistors of predetermined resistance ratio in a degenerative feedback loop so that the common emitter stage additionally provides a stabilized direct current voltage reference for the common collector stage.
Abstract:
PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
Abstract:
PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
Abstract:
Apparatus for performing spectral analysis comprises a cascade connection of low-pass sampling filters 100-1 to 100-N operated at successively lower sampling rates. Thus an input signal Go, which may be a video or an audio signal, is transformed into Loplacian component signals Lo to LN-1, and a remnant Gaussian output GN. The apparatus may be embodied in digital form wherein each of the filters comprises a digital convolution filter. In the alternative, analogue embodiments may employ charge coupled devices as convolution or interpolation filters. Apparatus is also disclosed for synthesising a signal by recombining the spectrum analysis components.