Transistor biasing arrangement
    11.
    发明授权
    Transistor biasing arrangement 失效
    晶体管偏置布置

    公开(公告)号:US3891935A

    公开(公告)日:1975-06-24

    申请号:US39948673

    申请日:1973-09-21

    Applicant: RCA CORP

    CPC classification number: H03F3/45479 G05F3/225 H03F1/302

    Abstract: A first biasing transistor has at least a portion of its base current supplied by the emitter current of a second biasing transistor. The collector current of the first transistor is larger than the collector current of the second transistor by a factor proportional to the hfe current gain characteristic of the first transistor. The collector current of the first transistor is used to establish the quiescent collector-to-emitter current flow of an amplifier transistor having an hfe which matches that of the first biasing transistor. The collector current of the second transistor is used to establish the level quiescent base current supplied to the amplifier for supporting the latter quiescent collector-to-emitter current flow. This avoids quiescent base current drain from the circuitry providing input signal to the amplifier transistor.

    Abstract translation: 第一偏置晶体管具有由第二偏置晶体管的发射极电流提供的其基极电流的至少一部分。 第一晶体管的集电极电流大于第二晶体管的集电极电流与第一晶体管的hfe电流增益特性成比例的因子。 第一晶体管的集电极电流被用于建立具有与第一偏置晶体管的hfe匹配的hfe的放大器晶体管的静态集电极 - 发射极电流。 第二晶体管的集电极电流用于建立提供给放大器的电平静态基极电流,用于支持后者的静态集电极到发射极的电流。 这避免了从提供输入信号到放大器晶体管的电路的静态基极电流漏极。

    Synchronous demodulator employing a common-base transistor amplifier
    12.
    发明授权
    Synchronous demodulator employing a common-base transistor amplifier 失效
    使用通用基极晶体管放大器的同步解调器

    公开(公告)号:US3673505A

    公开(公告)日:1972-06-27

    申请号:US3673505D

    申请日:1970-11-13

    Applicant: RCA CORP

    CPC classification number: H03D1/229

    Abstract: Input signals are coupled in common to the emitter electrodes of a pair of transistors arranged in a differential amplifier configuration, and are synchronously detected by switching signals coupled to the respective transistor base electrodes. The coupling to the emitter electrodes is through a transistor arranged in a common-base amplifier construction, with the signals to be demodulated being applied to the amplifier transistor emitter electrode via an included stabilizing resistor.

    Abstract translation: 输入信号共同耦合到以差分放大器配置布置的一对晶体管的发射极电极,并且通过耦合到各个晶体管基极的开关信号同步地检测。 与发射极电极的耦合是通过配置在共基放大器结构中的晶体管,被解调的信号经由包含的稳定电阻器施加到放大器晶体管发射极。

    Sample-and-hold circuit
    13.
    发明授权
    Sample-and-hold circuit 失效
    样品保持电路

    公开(公告)号:US3646362A

    公开(公告)日:1972-02-29

    申请号:US3646362D

    申请日:1970-04-30

    Applicant: RCA CORP

    CPC classification number: H03D13/006

    Abstract: A sample-and-hold circuit employs first and second transistors of the same conductivity type, having serially coupled collectorto-emitter current paths and including a feedback path coupling the collector of the first transistor to the base of the second transistor to provide a high-input impedance and a relatively low-output impedance circuit suitable for rapid updating of a hold capacitor. The circuit samples an applied signal when the first and second transistors are keyed into conduction by keying circuit means, and holds when these transistors are biased out of conduction. The circuit is particularly suited for application as a phase comparator.

    Abstract translation: 采样和保持电路采用具有相同导电类型的第一和第二晶体管,具有串联耦合的集电极到发射极电流路径,并且包括将第一晶体管的集电极耦合到第二晶体管的基极的反馈路径, 高输入阻抗和适用于快速更新保持电容的相对低输出阻抗电路。 当第一和第二晶体管通过键控电路装置键入导通时,电路对施加的信号进行采样,并且当这些晶体管偏置导通时,该信号保持。 该电路特别适合用作相位比较器。

    Electronic processing apparatus
    14.
    发明授权
    Electronic processing apparatus 失效
    电子加工设备

    公开(公告)号:US3629611A

    公开(公告)日:1971-12-21

    申请号:US3629611D

    申请日:1969-12-29

    Applicant: RCA CORP

    CPC classification number: H04B1/1653

    Abstract: Average detection apparatus employing pulse-stretching techniques for increasing the energy content and compressing the dynamic pulse width range of a pulse train including randomly occurring, short duration, widely spaced pulses. The pulse train and a train of reference pulses are supplied to a bistable storage element to set and reset the element, respectively, to first and second output states. An average detector is coupled to the output of the storage element.

    Electrical circuits
    15.
    发明授权
    Electrical circuits 失效
    电路

    公开(公告)号:US3555309A

    公开(公告)日:1971-01-12

    申请号:US3555309D

    申请日:1967-11-03

    Applicant: RCA CORP

    CPC classification number: G05F1/562 H03F3/347

    Abstract: An electrical circuit especially suited for fabrication using integrated circuit techniques including a common emitter transistor amplifier connected in cascade relation with a common collector transistor amplifier and interconnected with a pair of resistors of predetermined resistance ratio in a degenerative feedback loop so that the common emitter stage additionally provides a stabilized direct current voltage reference for the common collector stage.

    17.
    发明专利
    未知

    公开(公告)号:FR2560700A1

    公开(公告)日:1985-09-06

    申请号:FR8502983

    申请日:1985-02-28

    Applicant: RCA CORP

    Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.

    18.
    发明专利
    未知

    公开(公告)号:BR8403141A

    公开(公告)日:1985-06-11

    申请号:BR8403141

    申请日:1984-06-27

    Applicant: RCA CORP

    Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.

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