公开(公告)号：WO1991013405A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001254

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  KATZ, Randy, H. ,  POWERS, David, T. ,  JAFFE, David, H. ,  GLIDER, Joseph, S. ,  IDLEMAN, Thomas, E.

IPC: G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/08 ,  G06F11/1441 ,  G06F11/1443 ,  G06F2201/835 ,  G06F2211/104

Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.

公开(公告)号：WO1991014228A1

公开(公告)日：1991-09-19

申请号：PCT/US1991001716

申请日：1991-03-14

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  NGUYEN, Anh ,  GAJJAR, Kumar

IPC: G06F13/00

CPC classification number: G06F3/0601 ,  G06F13/124 ,  G06F2003/0691

Abstract: A data storage system having a local processor (28) and a plurality of memory storage elements (26) is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers (24), each coupled to a separate memory storage element (26). A data path control circuit (30) is programmed by the local processor (28) to control the transfer of data between the external CPUs and the memory buffers (24). Two interface circuits (16 and 18) are coupled between the external CPUs and the memory buffers (24) to provide two data paths for transferring data between the external CPUs and memory buffers (24). The data path control circuit (30) contains two independent sequencing circuits for selecting memory buffers (24). This allows one data path to be used for reading or writing to a number of the memory buffers (24) while the other data path is simultaneously used for a different operation for the rest of the memory buffers (24).

公开(公告)号：WO1991013404A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001252

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  JAFFE, David, H. ,  POWERS, David, T. ,  GAJJAR, Kumar ,  GLIDER, Joseph, S. ,  IDLEMAN, Thomas, E.

IPC: G06F11/10

CPC classification number: G06F11/2089 ,  G06F11/0757 ,  G06F11/1076 ,  G06F2211/103 ,  G11B20/1833

Abstract: A mass storage apparatus, made up of a plurality of physical storage devices, which is capable of providing both high bandwidth and high operation rate, as necessary, along with high reliability, is provided. The device set is divided into one or more redundancy groups. Each redundancy group is in turn divided into one or more data groups, each of which may span only a small number of the drives in the redundancy group, providing a high request rate, or which may span a large number of drives, providing high bandwidth.

公开(公告)号：WO1991013399A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001276

申请日：1991-02-28

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  IDLEMAN, Thomas, E. ,  KOONTZ, Robert, S. ,  POWERS, David, T. ,  JAFFE, David, H. ,  HENSON, Larry, P. ,  GLIDER, Joseph, S. ,  GAJJAR, Kumar

IPC: G06F07/22

CPC classification number: G06F11/10 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G11B20/1833

Abstract: A method and apparatus for controlling data flow between a computer (10) and a group of memory devices (18A-18F) arranged in a particular logical configuration. The system includes a group of first level controllers (12A, 12B) and a group of second level controllers (14A, 14B). The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry (16) which permits a functioning second level controller to assume control of a group of memory devices formely primarily controlled by the failed second level controller. In addition, the invention provides error check and correction (Figure 10) as well as mass storage device configuration circuitry.

公开(公告)号：WO1991013394A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001257

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  GLIDER, Joseph, S. ,  POWERS, David, T. ,  IDLEMAN, Thomas, E.

IPC: G06F03/06

CPC classification number: G06F3/0601 ,  G06F11/08 ,  G06F11/1076 ,  G06F11/1612 ,  G06F2003/0692 ,  G06F2211/1007 ,  G06F2211/104 ,  G11C29/70 ,  G11C29/88

Abstract: Methods and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. A method and apparatus is provided for detecting and reconstructing incorrectly routed data. A method and apparatus is also provided for detecting when one or more physical devices fails to write a block of data, and for reconstructing lost data.

公开(公告)号：WO1991001021A1

公开(公告)日：1991-01-24

申请号：PCT/US1990003594

申请日：1990-06-25

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  GAJJAR, Kumar ,  NGUYEN, Anh

IPC: G06F03/06

CPC classification number: G06F3/0601 ,  G06F1/03 ,  G06F2003/0692

Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.