公开(公告)号：WO1991015825A1

公开(公告)日：1991-10-17

申请号：PCT/US1991001255

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  GAJJAR, Kumar ,  SHAH, Kaushik, S. ,  TRANG, Duc, H.

IPC: G06F13/42

CPC classification number: G06F3/0601 ,  G06F13/4213 ,  G06F13/4226 ,  G06F2003/0692

Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Abstract translation: 提供了部分基于SCSI标准的改进的接口系统。 单个电缆数据总线同时在两个设备之间传输几个字节的信息。 接口系统在单个并行传输中传输多字节命令，消息，状态信息或数据。 提供微定序器以允许跨接口的数据传输，而不需要来自转移涉及的设备中的处理器的繁重的注意。

公开(公告)号：WO1991015824A1

公开(公告)日：1991-10-17

申请号：PCT/US1991002316

申请日：1991-04-03

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  HENSON, Larry, P. ,  GAJJAR, Kumar ,  IDLEMAN, Thomas, E.

IPC: G06F13/18

CPC classification number: G06F13/374 ,  G06F13/36

Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus (16), where the bus (16) has control and arbitration functions distributed among the devices (20) coupled to the bus (16), with each device (20) having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus (16) by a plurality of SCSI devices (20) coupled to the bus (16) by providing a pseudo busy signal to SCSI devices (20) from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices (20) and control the order in which the devices (20) will be serviced when ready.

Abstract translation: 本发明提供了一种用于动态地修改对总线（16）的访问的优先级的方法和装置，其中总线（16）具有分配在耦合到总线（16）的设备（20）中的控制和仲裁功能，每个 装置（20）具有固定的优先级。 选择性地禁止由特定设备访问总线，防止它们断言其固定的优先级。 在优选实施例中，本发明通过向SCSI设备（20）提供伪忙信号来提供通过耦合到总线（16）的多个SCSI设备（20）来重新选择SCSI总线（16）的控制，SCSI设备 不需要重新选择。 以这种方式，启动器可以向SCSI设备（20）发出多个命令，并且在准备好时控制设备（20）将被服务的顺序。

公开(公告)号：WO1991015822A1

公开(公告)日：1991-10-17

申请号：PCT/US1991002315

申请日：1991-04-03

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  HENSON, Larry, P. ,  GAJJAR, Kumar ,  POWERS, David, T. ,  IDLEMAN, Thomas, E.

IPC: G06F11/20

CPC classification number: G06F11/10 ,  G06F11/0757 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G06F2211/1057 ,  G11B20/1833

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives (250-255) coupled to a plurality of small buffers (240-245). An Error Correction Controller (260 and 270) is coupled to a plurality of X-bar switches (210-215), the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.

公开(公告)号：EP0518986A1

公开(公告)日：1992-12-23

申请号：EP91906226.0

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： JAFFE, David, H. ,  POWERS, David, T. ,  GAJJAR, Kumar ,  GLIDER, Joseph, S. ,  IDLEMAN, Thomas, E.

IPC: G06F3 ,  G06F11 ,  G06F12 ,  G11B20

CPC classification number: G06F11/2089 ,  G06F11/0757 ,  G06F11/1076 ,  G06F2211/103 ,  G11B20/1833

Abstract: Un appareil à mémoire de grande capacité, composé d'une pluralité de dispositifs physiques de mémorisation, permet d'obtenir tant une grande largeur de bande qu'une vitesse élevée d'exploitation, selon les besoins, ainsi qu'une haute fiabilité. L'ensemble de dispositifs est divisé en deux ou plusieurs groupes de redondance. Chaque groupe de redondance est à son tour divisé en deux ou plusieurs groupes de données dont chacun peut s'étendre uniquement sur un nombre réduit d'unités dans le groupe de redondance, ce qui permet d'obtenir une vitesse élevée de demande, ou peut s'étendre sur un grand nombre d'unités, ce qui permet d'obtenir une grande largeur de bande.

公开(公告)号：WO1991014228A1

公开(公告)日：1991-09-19

申请号：PCT/US1991001716

申请日：1991-03-14

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  NGUYEN, Anh ,  GAJJAR, Kumar

IPC: G06F13/00

CPC classification number: G06F3/0601 ,  G06F13/124 ,  G06F2003/0691

Abstract: A data storage system having a local processor (28) and a plurality of memory storage elements (26) is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers (24), each coupled to a separate memory storage element (26). A data path control circuit (30) is programmed by the local processor (28) to control the transfer of data between the external CPUs and the memory buffers (24). Two interface circuits (16 and 18) are coupled between the external CPUs and the memory buffers (24) to provide two data paths for transferring data between the external CPUs and memory buffers (24). The data path control circuit (30) contains two independent sequencing circuits for selecting memory buffers (24). This allows one data path to be used for reading or writing to a number of the memory buffers (24) while the other data path is simultaneously used for a different operation for the rest of the memory buffers (24).

公开(公告)号：WO1991013404A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001252

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  JAFFE, David, H. ,  POWERS, David, T. ,  GAJJAR, Kumar ,  GLIDER, Joseph, S. ,  IDLEMAN, Thomas, E.

IPC: G06F11/10

CPC classification number: G06F11/2089 ,  G06F11/0757 ,  G06F11/1076 ,  G06F2211/103 ,  G11B20/1833

Abstract: A mass storage apparatus, made up of a plurality of physical storage devices, which is capable of providing both high bandwidth and high operation rate, as necessary, along with high reliability, is provided. The device set is divided into one or more redundancy groups. Each redundancy group is in turn divided into one or more data groups, each of which may span only a small number of the drives in the redundancy group, providing a high request rate, or which may span a large number of drives, providing high bandwidth.

公开(公告)号：WO1991013399A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001276

申请日：1991-02-28

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  IDLEMAN, Thomas, E. ,  KOONTZ, Robert, S. ,  POWERS, David, T. ,  JAFFE, David, H. ,  HENSON, Larry, P. ,  GLIDER, Joseph, S. ,  GAJJAR, Kumar

IPC: G06F07/22

CPC classification number: G06F11/10 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G11B20/1833

Abstract: A method and apparatus for controlling data flow between a computer (10) and a group of memory devices (18A-18F) arranged in a particular logical configuration. The system includes a group of first level controllers (12A, 12B) and a group of second level controllers (14A, 14B). The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry (16) which permits a functioning second level controller to assume control of a group of memory devices formely primarily controlled by the failed second level controller. In addition, the invention provides error check and correction (Figure 10) as well as mass storage device configuration circuitry.

公开(公告)号：WO1991001021A1

公开(公告)日：1991-01-24

申请号：PCT/US1990003594

申请日：1990-06-25

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  GAJJAR, Kumar ,  NGUYEN, Anh

IPC: G06F03/06

CPC classification number: G06F3/0601 ,  G06F1/03 ,  G06F2003/0692

Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.

公开(公告)号：EP0517857A1

公开(公告)日：1992-12-16

申请号：EP91907076.0

申请日：1991-02-28

Applicant: SF2 CORPORATION

Inventor： IDLEMAN, Thomas, E. ,  KOONTZ, Robert, S. ,  POWERS, David, T. ,  JAFFE, David, H. ,  HENSON, Larry, P. ,  GLIDER, Joseph, S. ,  GAJJAR, Kumar

IPC: G06F3 ,  G06F11 ,  G11B20

CPC classification number: G06F11/10 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G11B20/1833

Abstract: Méthode et dispositif permettant de gérer le flux des données entre un ordinateur (10) et un ensemble de dispositifs de mémoire (18A-18F) disposés selon une configuration logique particulière. Le système comprend un groupe d'unités de contrôle du premier niveau (12A, 12B) et un groupe d'unités de contrôle du second niveau (14A, 14B). Les premières et les secondes fonctionnent ensemble de telle sorte que si l'une de celles du second niveau est défaillante, l'acheminement entre les unités du premier niveau et les dispositifs de mémoire est commuté sur une unité de contrôle du second niveau qui fonctionne correctement sans qu'il soit nécessaire que l'ordinateur intervienne dans la procédure de réachimenement. La configuration logique des dispositifs de mémoire reste constante. L'invention comporte également un ensemble de circuits de commutation (16) permettant qu'une unité de contrôle du second niveau fonctionnant correctement pilote un groupe de dispositifs de mémoire qui étaient antérieurement pilotés principalement par l'unité de contrôle défaillante du second niveau. En outre, l'invention comporte une vérification et correction d'erreur (fig. 10), ainsi qu'un ensemble de circuits de configuration de mémoire de grande capacité.

公开(公告)号：EP0479919A1

公开(公告)日：1992-04-15

申请号：EP90911794.0

申请日：1990-06-25

Applicant: SF2 CORPORATION

Inventor： GAJJAR, Kumar ,  NGUYEN, Anh

IPC: G06F1 ,  G06F3

CPC classification number: G06F3/0601 ,  G06F1/03 ,  G06F2003/0692

Abstract: L'invention concerne un circuit de sélection programmable de séquences d'éléments qui permet de sélectionner une séquence répétitive d'éléments à partir d'une pluralité d'éléments. Le circuit de sélection de séquences comprend un circuit de stockage de séquences dans lequel on charge une séquence d'identificateurs d'éléments à laquelle on peut avoir accès.