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公开(公告)号：FR2507366A1
公开(公告)日：1982-12-10
申请号：FR8209781
申请日：1982-06-04
Applicant: SONY CORP
Inventor： SONEDA MITSUO , OTSU TAKAJI
Abstract: A liquid crystal matrix display device has a plurality of display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to improve the resolution without sacrifice of contrast, the vertical transmitting lines are arranged into groups of a predetermined number of such lines, and the input switching elements associated with the lines of each such group have their control electrodes coupled together to a respective output of the horizontal scanning pulse generator. The input circuit includes time-demultiplexing circuitry, for example, formed of sample/hold circuits, to present respective sampled versions of the input signal, staggered with respect to one another, to input electrodes of respective ones of the input switching devices of each of the groups.
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公开(公告)号：DE3000933A1
公开(公告)日：1980-07-24
申请号：DE3000933
申请日：1980-01-11
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAO , SONEDA MITSUO
IPC: G11C27/04 , G11C19/28 , G11C27/00 , H01L21/339 , H01L29/76 , H01L29/762 , H01L29/772 , H03H7/30 , H03H15/02 , H03H7/28
Abstract: A filter circuit of the type utilizing a charge-transfer device, such as a bucket brigade device, comprises a clocking signal drive circuit for supplying a clocking signal; a clock signal generator at whose output a clocking control signal is provided; a transistor whose base is connected to the output of the clock signal generator; a plurality of successive capacitive storage stages for sequentially holding a charge level representing a time-sampled input signal, each of the capacitive storage stages having a clocking electrode for receiving the clocking signal so that the charge level is transferred from one to another of the capacitive storage stages in succession, and at least one of the capacitive storage stages being formed of first and second parallel-connected capacitive circuit portions, and the first and second capacitive circuit portions having respective clocking electrodes coupled to the clock signal generator and to the emitter of the transistor, respectively; and a current feedback circuit, such as a current mirror circuit, for detecting the current flowing through the collector of the transistor and applying a corresponding current to a capacitive storage stage in advance of that stage which is coupled to the emitter of the transistor.
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公开(公告)号：SG48486A1
公开(公告)日：1998-04-17
申请号：SG1996011077
申请日：1996-11-07
Applicant: SONY CORP
Inventor： SONEDA MITSUO , LI AKIRA
Abstract: An internal power supply circuit, comprising a plurality of charge accumulators (C1 - C3), a first power supply terminal (Vcc), a second power supply terminal (GND), a first switch (NUi, NLi) for connecting the plurality of charge accumulators in parallel to each other in a first state, and a second switch (PT1 - PT3) for connecting the plurality of charge accumulators in series with each other in a second state, the charge accumulators connected between the first power supply terminal and the second power supply terminal at the first state and the first state and the second state set repeatedly to raise a voltage between the first power supply terminal and the second power supply terminal.
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公开(公告)号：DE3781193T2
公开(公告)日：1993-03-18
申请号：DE3781193
申请日：1987-04-22
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: G11C11/419 , G11C7/06 , G11C11/409
Abstract: A sense amplifier (11) includes two cross-coupled field effect transistors (M1, M2) coupled by capacitors (C1, C2) to respective bit lines (BL2, BL1) from a memory cell. During a precharging operation, the capacitors (C1, C2) are charged to precharged voltages indicative of the threshold dispersion voltage between the two transistors (M1, M2). Thereafter, during a sensing operation, the precharged voltages are applied to the gates (G1, G2) of the transistors (M1, M2) to compensate for the threshold dispersion voltage.
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公开(公告)号：DE3781193D1
公开(公告)日：1992-09-24
申请号：DE3781193
申请日：1987-04-22
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: G11C11/419 , G11C7/06 , G11C11/409
Abstract: A sense amplifier (11) includes two cross-coupled field effect transistors (M1, M2) coupled by capacitors (C1, C2) to respective bit lines (BL2, BL1) from a memory cell. During a precharging operation, the capacitors (C1, C2) are charged to precharged voltages indicative of the threshold dispersion voltage between the two transistors (M1, M2). Thereafter, during a sensing operation, the precharged voltages are applied to the gates (G1, G2) of the transistors (M1, M2) to compensate for the threshold dispersion voltage.
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Patent Agency Ranking
公开(公告)号：FR2506546B1
公开(公告)日：1988-11-04
申请号：FR8208913
申请日：1982-05-21
Applicant: SONY CORP
Inventor： SONEDA MITSUO , NOGUCHI TAKASHI , OHTSU TAKAJI
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公开(公告)号：GB2103857B
公开(公告)日：1984-09-05
申请号：GB8216599
申请日：1982-06-08
Applicant: SONY CORP
Inventor： KUTARAGI KEN , OTSU TAKAJI , SONEDA MITSUO
Abstract: A liquid crystal matrix display device has a plurality of liquid crystal display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to compensate for crosstalk that occurs because of parasitic capacitance between the vertical transmitting lines and the liquid crystal display elements, auxiliary lines are provided for the columns of such display elements, and each has a predetermined compensating capacitance relative to its associated liquid crystal display elements. A compensating signal, which is an inverted version of the video signal, is applied in succession to the auxiliary lines to compensate for any crosstalk.
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公开(公告)号：GB2130036A
公开(公告)日：1984-05-23
申请号：GB8323730
申请日：1983-09-05
Applicant: SONY CORP
Inventor： SONEDA MITSUO , MAEKAWA TOSHIKAZU , OTSU KOUJI
Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage. Furthermore, a second transmission gate is connected between the output terminal of the source follower transistor and the ground in which after the output signal at the output terminal rises up and falls down once, the second transmission gate is turned on by the signal relating to the output from the stages following the succeeding stage to thereby make the level of the signal when the output signal at the output terminal falls down stable. Thus, undesired potential fluctuation is not generated on the output line.
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公开(公告)号：AU533668B2
公开(公告)日：1983-12-08
申请号：AU5440380
申请日：1980-01-07
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAO , SONEDA MITSUO
IPC: G11C27/04 , G11C19/28 , G11C27/00 , H01L21/339 , H01L29/76 , H01L29/762 , H01L29/772 , H03H7/30 , H03H15/02 , H03H11/26
Abstract: A filter circuit of the type utilizing a charge-transfer device, such as a bucket brigade device, comprises a clocking signal drive circuit for supplying a clocking signal; a clock signal generator at whose output a clocking control signal is provided; a transistor whose base is connected to the output of the clock signal generator; a plurality of successive capacitive storage stages for sequentially holding a charge level representing a time-sampled input signal, each of the capacitive storage stages having a clocking electrode for receiving the clocking signal so that the charge level is transferred from one to another of the capacitive storage stages in succession, and at least one of the capacitive storage stages being formed of first and second parallel-connected capacitive circuit portions, and the first and second capacitive circuit portions having respective clocking electrodes coupled to the clock signal generator and to the emitter of the transistor, respectively; and a current feedback circuit, such as a current mirror circuit, for detecting the current flowing through the collector of the transistor and applying a corresponding current to a capacitive storage stage in advance of that stage which is coupled to the emitter of the transistor.
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公开(公告)号：FR2506546A1
公开(公告)日：1982-11-26
申请号：FR8208913
申请日：1982-05-21
Applicant: SONY CORP
Inventor： SONEDA MITSUO , NOGUCHI TAKASHI , OHTSU TAKAJI
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