公开(公告)号：FR3010829B1

公开(公告)日：2017-01-27

申请号：FR1359026

申请日：2013-09-19

Applicant: ST MICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MARTY MICHEL ,  JOUAN SEBASTIEN ,  FREY LAURENT

IPC: H01L21/70 ,  G02B5/20 ,  H01L23/552

公开(公告)号：FR3009888B1

公开(公告)日：2015-09-18

申请号：FR1358139

申请日：2013-08-23

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  FREY LAURENT ,  JOUAN SEBASTIEN ,  BOUTAMI SALIM

IPC: H01L31/02

公开(公告)号：FR2813707B1

公开(公告)日：2002-11-29

申请号：FR0011419

申请日：2000-09-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

公开(公告)号：FR2801420B1

公开(公告)日：2002-04-12

申请号：FR9914746

申请日：1999-11-23

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L29/732

Abstract: Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector on a layer of extrinsic collector in a semiconductor substrate; (b) making a lateral isolating region; (c) making a base next to he intrinsic collector and the lateral isolating region; and (d) making a bipartite dope emitter in situ. Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector (4) on a layer of extrinsic collector (2) in a semiconductor substrate (1); (b) making a lateral isolating region (5) surrounding the upper part of the intrinsic collector and of wells of the imprisoned extrinsic collector (60); (c) making a base (8) next to he intrinsic collector and the lateral isolating region and comprising a non-selective epitaxy of a semiconductor region (8) comprising at least one layer of silicon; (d) making a bipartite dope emitter (11) in situ comprising: (i) making a first layer (110) of the emitter formed from microcrystalline silicon and directly in contact with a part (800) of the upper surface of the semiconductor region situated on top of the intrinsic collector; and (ii) making a second part (111) of emitter from polycrystalline silicon; the two parts (110, 111) being separated by an oxide layer (112).