15.
    发明专利
    未知

    公开(公告)号:AT542240T

    公开(公告)日:2012-02-15

    申请号:AT09777658

    申请日:2009-08-05

    Inventor: PAGANI ALBERTO

    Abstract: A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

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