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    7.
    发明专利
    未知

    公开(公告)号：IT1319841B1

    公开(公告)日：2003-11-03

    申请号：ITTO20000146

    申请日：2000-02-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZANUCCOLI MAURO ,  CANEGALLO ROBERTO ,  DOZZA DAVIDE

    IPC: H02M3/07

    Abstract: A voltage boosting device having a charge pump circuit formed by a plurality of voltage boosting stages cascade-connected together. Each voltage boosting stage is connected to the adjacent stages via a first transfer node and a second transfer node and includes a storage capacitor connected at a terminal thereof to the second transfer node and receiving on the other terminal a first phase signal switching between a first value and a second value; a switch element including an NMOS transistor connected between the first transfer node and the second transfer node; a voltage boosting capacitor connected at a terminal thereof to the control terminal of the switch element and receiving on the other terminal a second phase signal; a first precharge circuit connected between the first transfer node and the control terminal of the switch element so as to control charge transfer from the first transfer node to the second transfer node when activated by a first activation signal; and a second precharge circuit connected between the second transfer node and the control terminal of the switch element so as to control charge transfer from the second transfer node to the first transfer node when activated by a second activation signal. The first activation signal and second activation signal are never active simultaneously.

    8.
    发明专利
    未知

    公开(公告)号：ITTO980961A1

    公开(公告)日：2000-05-15

    申请号：ITTO980961

    申请日：1998-11-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C16/12

    Abstract: The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.

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