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    17.
    发明专利
    未知

    公开(公告)号：ITRM20010282A1

    公开(公告)日：2002-11-25

    申请号：ITRM20010282

    申请日：2001-05-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

    IPC: G11C16/24 ,  G11C16/28

    Abstract: A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line. First and second resistive elements are also connected between the first and second transistors and the respective bit line.

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