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公开(公告)号:DE60041823D1
公开(公告)日:2009-04-30
申请号:DE60041823
申请日:2000-12-29
Applicant: ST MICROELECTRONICS SRL
Inventor: GASTALDI ROBERTO , LO GIUDICE GIANBATTISTA , PASOTTI MARCO , PIO FEDERICO
IPC: G11C16/10
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公开(公告)号:ITMI20011231A1
公开(公告)日:2002-12-12
申请号:ITMI20011231
申请日:2001-06-12
Applicant: ST MICROELECTRONICS SRL
Inventor: CONTE ANTONIO , LO GIUDICE GIANBATTISTA , SIGNORELLO ALFREDO
IPC: G11C16/28
Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
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公开(公告)号:DE602006009091D1
公开(公告)日:2009-10-22
申请号:DE602006009091
申请日:2006-07-06
Applicant: ST MICROELECTRONICS SRL
Inventor: CASTALDO ENRICO , CONTE ANTONINO , LO GIUDICE GIANBATTISTA
Abstract: There is disclosed an integrated control circuit (3) for a charge pump (1). The integrated circuit comprises a first device (112,N1,N2,R,12) suitable for regulating the output voltage (Vout) of the charge pump (1) and a second device (113,M10,M11,C11,11) suitable for increasing the output voltage (Vout) from the charge pump with a set ramp. The integrated circuit comprises means (111) suitable for activating said first device and providing it with a first value of a supply signal (Ireg) in a first period of time (A) and suitable for activating said second device and for providing it with a second value (Iramp) of the supply signal that is greater than the first value in a second period of time (C) after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value (Vlow) to a second value (Vhigh) that is greater than the first value, said second value being fixed by the reactivation of the first device.
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公开(公告)号:IT201600121618A1
公开(公告)日:2018-05-30
申请号:IT201600121618
申请日:2016-11-30
Applicant: ST MICROELECTRONICS SRL , ST MICROELECTRONICS ROUSSET
Inventor: GRANDE FRANCESCA , LA ROSA FRANCESCO , LO GIUDICE GIANBATTISTA , MATRANGA GIOVANNI
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公开(公告)号:FR2908919B1
公开(公告)日:2014-03-07
申请号:FR0759104
申请日:2007-11-16
Applicant: ST MICROELECTRONICS SRL
Inventor: CONTE ANTONIO , MICCICHE MARIO , LO GIUDICE GIANBATTISTA , DI MARTINO ALBERTO , SBERNO GIAMPIERO
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公开(公告)号:ITMI20062211A1
公开(公告)日:2008-05-18
申请号:ITMI20062211
申请日:2006-11-17
Applicant: ST MICROELECTRONICS SRL
Inventor: CONTE ANTONINO , DEMANGE NICOLAS , DI MARTINO ALBERTO , LO GIUDICE GIANBATTISTA , MICCICHE MARIO
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公开(公告)号:ITMI20062068A1
公开(公告)日:2008-04-28
申请号:ITMI20062068
申请日:2006-10-27
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号:ITMI20011231D0
公开(公告)日:2001-06-12
申请号:ITMI20011231
申请日:2001-06-12
Applicant: ST MICROELECTRONICS SRL
Inventor: CONTE ANTONIO , LO GIUDICE GIANBATTISTA , SIGNORELLO ALFREDO
IPC: G11C16/28
Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
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