公开(公告)号：FR2790893A1

公开(公告)日：2000-09-15

申请号：FR9903261

申请日：1999-03-12

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL

IPC: G06F17/30 ,  H04L49/111 ,  H04Q11/04 ,  H04L12/66

Abstract: The system uses a memory to retain indices and associated addresses for rapid identification of addresses. The system is intended to associate indices with addresses, selecting from a large number of available indices. It includes a memory (30) containing the indices and respective verification words corresponding to the predetermined bits of the addresses associated with the index. A compacting circuit (39) receives a current address (A) and suppresses within this address the bits determined by a pattern (41), such that the suppressed bits correspond to the verification word bits. The compacted address provided by the compacting circuit serves to select a reading position within the memory. A comparator (45) indicates that the current address corresponds to the selected memory position if the bits of the verification word are equal to the corresponding bits of the current address.

公开(公告)号：FR2789249A1

公开(公告)日：2000-08-04

申请号：FR9901192

申请日：1999-01-29

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/66

公开(公告)号：FR2787600A1

公开(公告)日：2000-06-23

申请号：FR9816156

申请日：1998-12-17

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/56

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management

公开(公告)号：DE69924217T2

公开(公告)日：2006-03-30

申请号：DE69924217

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  H04Q11/04 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management

公开(公告)号：FR2837586A1

公开(公告)日：2003-09-26

申请号：FR0203626

申请日：2002-03-22

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  FURODET DAVID

IPC: H04L29/12 ,  G06F12/02 ,  H04L12/56

Abstract: A table of addresses (14) is directly addressable by reduced addresses (RAD) associated with equipment/domain data pairs (MAC/VID). Flags indicate if an intermediate address is already linked to a data pair. For a data pair (MAC/VID(A)) an intermediate address (MAC2LINEAR(A)) with flag zoro may be adopted but for a data pair (MAC/VID(B)) flag 1 a second intermediate address (MAC2CRC32(B)) must be selected

公开(公告)号：FR2787600B1

公开(公告)日：2001-11-16

申请号：FR9816156

申请日：1998-12-17

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/56

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management

公开(公告)号：FR2789195B1

公开(公告)日：2001-09-21

申请号：FR9901191

申请日：1999-01-29

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL

IPC: H04L13/08 ,  H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  G06F15/163 ,  H04L29/06 ,  G06F13/40

Abstract: The concurrent digital rate transmission regulation technique has a high priority message sent to a file index (18a). An index is generated for the digital rate. A second lower priority message (18b) and is sent to a second file. The first file positions are successively examined and the position freed by sending the files to a distant position. The second file positions are then examined, whilst waiting for the indication of the digital rate for the first file and inscribing to the distant position the value of the digital rate for transmission of the first file.

公开(公告)号：FR2790893B1

公开(公告)日：2001-06-15

申请号：FR9903261

申请日：1999-03-12

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL

IPC: G06F17/30 ,  H04L49/111 ,  H04Q11/04 ,  H04L12/66

Abstract: The system uses a memory to retain indices and associated addresses for rapid identification of addresses. The system is intended to associate indices with addresses, selecting from a large number of available indices. It includes a memory (30) containing the indices and respective verification words corresponding to the predetermined bits of the addresses associated with the index. A compacting circuit (39) receives a current address (A) and suppresses within this address the bits determined by a pattern (41), such that the suppressed bits correspond to the verification word bits. The compacted address provided by the compacting circuit serves to select a reading position within the memory. A comparator (45) indicates that the current address corresponds to the selected memory position if the bits of the verification word are equal to the corresponding bits of the current address.

公开(公告)号：FR2789195A1

公开(公告)日：2000-08-04

申请号：FR9901191

申请日：1999-01-29

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL

IPC: H04L13/08 ,  H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  G06F15/163 ,  H04L29/06 ,  G06F13/40

Abstract: The concurrent digital rate transmission regulation technique has a high priority message sent to a file index (18a). An index is generated for the digital rate. A second lower priority message (18b) and is sent to a second file. The first file positions are successively examined and the position freed by sending the files to a distant position. The second file positions are then examined, whilst waiting for the indication of the digital rate for the first file and inscribing to the distant position the value of the digital rate for transmission of the first file.