公开(公告)号：JP2000224238A

公开(公告)日：2000-08-11

申请号：JP2000020024

申请日：2000-01-28

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/56 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To obtain a system that manages data transmission on a single channel from a plurality of data transmitters. SOLUTION: A data source data transmission system is a system that transmits a request with usual priority when a data source is ready for transmission of a data packet, and includes a round robin circuit 12 that causes packet transmission by a data source being a request presentation object before present analysis time by checking a request in a consecutive analysis time. This system includes a queue having two positions to which a packet is soon written for each data source when the data source is ready, and when the queue includes a single packet, a request with usual priority is presented and the queue includes two packets, the request with higher priority is presented and transmission of the packet of each queue relating to the request with higher priority is caused and when the request with higher priority is not presented before the analysis time, the round robin circuit 12 is used only to cause the transmission of the packet of the queue relating to the request with the usual priority.

公开(公告)号：JP2000236354A

公开(公告)日：2000-08-29

申请号：JP35731699

申请日：1999-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/56 ,  H04L12/28 ,  H04L12/46

Abstract: PROBLEM TO BE SOLVED: To optimize access to a queue of idle blocks by filling a cache memory, including a partial queue of exclusively used idle blocks, from a main queue by a burst when its filling level reaches the lowest limit and emptying it for the main queue by the burst when the filling level reaches the highest limit. SOLUTION: The cache memory 20 is preferably an LIFO type. To manage the cache memory 20 of this type, a controller CTRL includes a register including a pointer topc indicating the uppermost part of the cache memory 20. When the pointer topc reaches the highest limit max, part of the contents of the cache memory 20 is transferred to an idle block queue 18 by the burst. When the pointer topc reaches the lowest limit min to the contrary, part of the idle block queue 18 is transferred by the burst to the cache memory 20.

公开(公告)号：FR2789249A1

公开(公告)日：2000-08-04

申请号：FR9901192

申请日：1999-01-29

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/66

公开(公告)号：FR2787600A1

公开(公告)日：2000-06-23

申请号：FR9816156

申请日：1998-12-17

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/56

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management

公开(公告)号：DE69924217D1

公开(公告)日：2005-04-21

申请号：DE69924217

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management

公开(公告)号：DE69924217T2

公开(公告)日：2006-03-30

申请号：DE69924217

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  H04Q11/04 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management

公开(公告)号：FR2787600B1

公开(公告)日：2001-11-16

申请号：FR9816156

申请日：1998-12-17

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/56

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management