公开(公告)号：JP2000332795A

公开(公告)日：2000-11-30

申请号：JP2000066967

申请日：2000-03-10

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL

IPC: G06F17/30 ,  H04L12/70 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To improve speediness and data cost by making a new address correspond to a memory storage location when the bits of a check word in a selected memory location are equal to the corresponding bits of the new address in read mode by using a packed address. SOLUTION: Each word in a memory 30 includes a 10-bit index for identifying a connection, an effective bit, indicating whether a storage location is used for the connection, and a check word of the most significant 20 bits of the address of the connection made to correspond to the storage location. A comparator 45 compares bits which are extracted from the address A and suppressed, by packing with the bits of the check word read out of the selected storage location. When they are equal, the address A copes with the connection of the selected storage location, and the index in the storage location identifies the connection.

公开(公告)号：JP2000224200A

公开(公告)日：2000-08-11

申请号：JP2000020023

申请日：2000-01-28

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL

IPC: H04L13/08 ,  H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To control the speed of multiplex transmission, having different speed restrictions on the same communication channel by writing an index corresponding to transmission having a high priority order in a first queue and writing the index, corresponding to transmission having a lower priority order in a second queue. SOLUTION: The connection written in a queue 18a is processed by the priority order related to connection which is written in a queue 18b. A connection to which the high priority order has to be assigned (CBR connection and real-time VBR connection) is written in the queue 18a, and other connections (VBR connection which is not in real-time, ABR connection and UBR connection) are written in the queue 18b. The queue 18a includes multiple continuous indexes so that a ghost index is written, in order to avoid the situation in which the connection of the queue 18b is not processed in time. The method avoides concentration of the continuous indexes in the queue 18a and enables processing periodically in the queue 18b.

公开(公告)号：JP2000236354A

公开(公告)日：2000-08-29

申请号：JP35731699

申请日：1999-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/56 ,  H04L12/28 ,  H04L12/46

Abstract: PROBLEM TO BE SOLVED: To optimize access to a queue of idle blocks by filling a cache memory, including a partial queue of exclusively used idle blocks, from a main queue by a burst when its filling level reaches the lowest limit and emptying it for the main queue by the burst when the filling level reaches the highest limit. SOLUTION: The cache memory 20 is preferably an LIFO type. To manage the cache memory 20 of this type, a controller CTRL includes a register including a pointer topc indicating the uppermost part of the cache memory 20. When the pointer topc reaches the highest limit max, part of the contents of the cache memory 20 is transferred to an idle block queue 18 by the burst. When the pointer topc reaches the lowest limit min to the contrary, part of the idle block queue 18 is transferred by the burst to the cache memory 20.

公开(公告)号：JP2000224238A

公开(公告)日：2000-08-11

申请号：JP2000020024

申请日：2000-01-28

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/56 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To obtain a system that manages data transmission on a single channel from a plurality of data transmitters. SOLUTION: A data source data transmission system is a system that transmits a request with usual priority when a data source is ready for transmission of a data packet, and includes a round robin circuit 12 that causes packet transmission by a data source being a request presentation object before present analysis time by checking a request in a consecutive analysis time. This system includes a queue having two positions to which a packet is soon written for each data source when the data source is ready, and when the queue includes a single packet, a request with usual priority is presented and the queue includes two packets, the request with higher priority is presented and transmission of the packet of each queue relating to the request with higher priority is caused and when the request with higher priority is not presented before the analysis time, the round robin circuit 12 is used only to cause the transmission of the packet of the queue relating to the request with the usual priority.

公开(公告)号：FR2837587B1

公开(公告)日：2008-04-11

申请号：FR0203628

申请日：2002-03-22

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  FURODET DAVID

IPC: G06F12/02 ,  G06F13/38 ,  G06F15/173 ,  H04L12/54 ,  H04L12/747

Abstract: An index (IND) is provided by a module (10) which contains one bit equipment presence indicators organized as words (Wi) and includes a pointer (ADP) generated from an equipment address and virtual domain. At any pointer position the index is the sum of the base value (Bvi) of the associated word and the number of positive indicators remaining to the pointer position. The index is used to access a context memory (12) An Independent claim is also included for : A circuit which includes a module and address pointer able to provide an index which is used to access a context memory.

公开(公告)号：FR2895176B1

公开(公告)日：2008-02-22

申请号：FR0513072

申请日：2005-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： FRANCILLON AURELIEN ,  ROCA VINCENT ,  NEUMANN CHRISTOPH ,  MONIOT PASCAL

IPC: H04L1/22 ,  H03M13/03 ,  H04L9/28 ,  H04N7/16

公开(公告)号：DE69924217D1

公开(公告)日：2005-04-21

申请号：DE69924217

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04

Abstract: A memory controller (12) manages allocation of block to chains of blocks. A memory cache (20) contains a partial set of free blocks that the controller uses exclusively in its management. A memory cache may be filled by a burst from a main line when its filling level reaches a minimal limit, and inflow may be ceased when its filling level reaches a maximal limit. An Independent claim is included for: (a) a method of a memory management

公开(公告)号：FR2895176A1

公开(公告)日：2007-06-22

申请号：FR0513072

申请日：2005-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： FRANCILLON AURELIEN ,  ROCA VINCENT ,  NEUMANN CHRISTOPH ,  MONIOT PASCAL

IPC: H04L1/22 ,  H03M13/03 ,  H04L9/28 ,  H04N7/16

Abstract: L'invention concerne un procédé et un système de codage de données numériques (DATA) représentées par des symboles source, par un code correcteur d'erreur de génération de symboles de parité à partir, pour chaque symbole de parité, de plusieurs symboles source et d'au moins un symbole de parité de rang précédent, comportant au moins un chiffrement (54) d'au moins une première valeur (P1) en plusieurs valeurs chiffrées et une prise en compte d'au moins une combinaison (P1,j) desdites valeurs chiffrées pour calculer (55) au moins une partie (P2...Pn-k) des symboles de parité.

公开(公告)号：FR2837586B1

公开(公告)日：2005-03-18

申请号：FR0203626

申请日：2002-03-22

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  FURODET DAVID

IPC: H04L29/12 ,  G06F12/02 ,  H04L12/56

Abstract: A table of addresses (14) is directly addressable by reduced addresses (RAD) associated with equipment/domain data pairs (MAC/VID). Flags indicate if an intermediate address is already linked to a data pair. For a data pair (MAC/VID(A)) an intermediate address (MAC2LINEAR(A)) with flag zoro may be adopted but for a data pair (MAC/VID(B)) flag 1 a second intermediate address (MAC2CRC32(B)) must be selected

公开(公告)号：FR2837587A1

公开(公告)日：2003-09-26

申请号：FR0203628

申请日：2002-03-22

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  FURODET DAVID

IPC: G06F12/02 ,  G06F13/38 ,  G06F15/173 ,  H04L12/54 ,  H04L12/747 ,  H04L12/56

Abstract: An index (IND) is provided by a module (10) which contains one bit equipment presence indicators organized as words (Wi) and includes a pointer (ADP) generated from an equipment address and virtual domain. At any pointer position the index is the sum of the base value (Bvi) of the associated word and the number of positive indicators remaining to the pointer position. The index is used to access a context memory (12) An Independent claim is also included for : A circuit which includes a module and address pointer able to provide an index which is used to access a context memory.