公开(公告)号：DE69506656T2

公开(公告)日：1999-05-20

申请号：DE69506656

申请日：1995-09-26

Applicant: ST MICROELECTRONICS SA

Inventor： PAVLIN ANTOINE

IPC: H02M3/28 ,  H02M3/335 ,  H02M3/338

Abstract: The load (RL) - e.g., a battery - is connected across an output winding (12) on an iron core (13), magnetised by the input winding (11) current (I1). A diode (D) prevents transformer action (I2 - O). Current increases till the voltage (KI1) across a small series resistor (20) equals a reference value (Vr), provided by an auxiliary switched circuit (VCC, Cr, Rr, S1). Comparator (24) output (R) causes a controlling bistable (22) to open a solid-state switch (S), interrupting the current. Load current (I2) then flows while the core demagnetises, till a detector (26), monitoring the voltage at the switched end of the input winding, causes the bistable to reclose the switch (S). Operation continues on this cycle, the mean load current provided depending on the cyclic switching ratio.

公开(公告)号：DE69834451D1

公开(公告)日：2006-06-14

申请号：DE69834451

申请日：1998-05-22

Applicant: ST MICROELECTRONICS SA

Inventor： BARRET JEAN ,  PAVLIN ANTOINE ,  FICHERA PIETRO

IPC: H01L27/02 ,  H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

公开(公告)号：DE69532315D1

公开(公告)日：2004-01-29

申请号：DE69532315

申请日：1995-09-25

Applicant: ST MICROELECTRONICS SA

Inventor： SIAUDEAU JEAN-LOUIS ,  PAVLIN ANTOINE

IPC: H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H03K17/16 ,  H03K17/56 ,  H03K17/64

Abstract: Two external terminals (Vcc, G) are connected to the positive supply and ground. Control voltages (V1, V3) switch first and second vertical MOS transistors (S1, S3). A third control voltage (V4) switches a lateral MOS transistor (S4) whose source and drain are connected to ground and to the vertical bipolar transistor base (T). An alternative directly replaces the vertical MOS transistors with npn bipolar transistors. The integrated circuit forming these components has an n-type material substrate whose rear part is highly doped and covered by a metallisation. There are cells for each vertical MOS transistor, a region for the bipolar transistor and enclosed blocks in the substrate for the zener diode and lateral MOS transistor. Metallisations interconnect the components.