公开(公告)号：FR2783981B1

公开(公告)日：2000-12-08

申请号：FR9812395

申请日：1998-09-29

Applicant: ST MICROELECTRONICS SA

Inventor： RIVET BERTRAND ,  PEZZANI ROBERT

IPC: H02H9/00 ,  H02M1/08 ,  H02M5/257 ,  H05B39/02 ,  H05B39/04 ,  H02M5/22 ,  H02M1/16

Abstract: The invention concerns a control circuit for controlling a load to be supplied in alternating current voltage, comprising a two-way switch capable of being controlled by phase angle, in series with the load between two terminals applying the alternating current supply, and comprising, in parallel with the switch, a first resistive element, a first capacitor and an element, in series with the first resistive element and the first capacitor, and operating, in steady state conditions, as a constant current source, the midpoint of the association in series connection of the first resistive element and the first capacitor being connected, via an element with two-way conduction automatically triggered when the voltage at its terminals exceeds a predetermined threshold, to a terminal controlling the switch.

公开(公告)号：DE69325241T2

公开(公告)日：2000-01-27

申请号：DE69325241

申请日：1993-11-29

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS INC

Inventor： PEZZANI ROBERT ,  UGGE ANGELO

IPC: H01L21/822 ,  H01L27/04 ,  H01L27/02 ,  H01L29/747 ,  H01L29/861 ,  H02H3/20 ,  H02H7/20

Abstract: The present invention relates to a circuit for protection against overvoltages comprising, in a substrate (62) with a first type of conductivity, first and second regions (38, 40) with the second type of conductivity; third and fourth regions (44, 46) with the first type of conductivity, formed in the first and the second region, respectively, and comprising subregions (50) through which parts of the first and second regions, respectively, are exposed; a fifth region (52) with the second type of conductivity; a sixth region (56) with the first type of conductivity in the fifth region, this sixth region also comprising subregions (58) through which parts of the fifth region are exposed. The hole density of the subregions of the sixth region is at least two to three times lower than the hole density of the subregions of the third and fourth regions.

公开(公告)号：DE69325241D1

公开(公告)日：1999-07-15

申请号：DE69325241

申请日：1993-11-29

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS INC

Inventor： PEZZANI ROBERT ,  UGGE ANGELO

IPC: H01L21/822 ,  H01L27/04 ,  H01L27/02 ,  H01L29/747 ,  H01L29/861 ,  H02H3/20 ,  H02H7/20

Abstract: The present invention relates to a circuit for protection against overvoltages comprising, in a substrate (62) with a first type of conductivity, first and second regions (38, 40) with the second type of conductivity; third and fourth regions (44, 46) with the first type of conductivity, formed in the first and the second region, respectively, and comprising subregions (50) through which parts of the first and second regions, respectively, are exposed; a fifth region (52) with the second type of conductivity; a sixth region (56) with the first type of conductivity in the fifth region, this sixth region also comprising subregions (58) through which parts of the fifth region are exposed. The hole density of the subregions of the sixth region is at least two to three times lower than the hole density of the subregions of the third and fourth regions.

公开(公告)号：DE69324952D1

公开(公告)日：1999-06-24

申请号：DE69324952

申请日：1993-03-17

Applicant: ST MICROELECTRONICS SA

Inventor： PEZZANI ROBERT

IPC: H01L21/332 ,  H01L29/08 ,  H01L29/74 ,  H01L29/747 ,  H01L29/87 ,  H03K17/725 ,  H01L29/86

Abstract: The present invention relates to a switch for AC voltage comprising, between first and second main terminals (A1, A2), a first thyristor (Th1) in anti-parallel configuration with a first diode (D1) and in series with a second thyristor (Th2) in anti-parallel configuration with a second diode (D2). The first thyristor has a control terminal (G) connected to its trigger region. The second thyristor and the second diode are made vertically in a common substrate and their conduction regions are tightly nested, from which it follows that a reversal of polarity following a period of conduction of the second diode causes the second thyristor to conduct.

公开(公告)号：DE69728937D1

公开(公告)日：2004-06-09

申请号：DE69728937

申请日：1997-07-24

Applicant: ST MICROELECTRONICS SA

Inventor： PEZZANI ROBERT ,  BERNIER ERIC

IPC: H01L29/73 ,  H01L21/331 ,  H01L27/06 ,  H01L29/732 ,  H01L29/74 ,  H01L29/744

Abstract: The structure includes an isolation wall (6) of a first conductivity type,formed in a semiconductor wafer (1) of a second conductivity type, separating a first portion of the wafer containing a high voltage thyristor with a layer corresponding to the wafer thickness, from a second portion containing logic circuit elements. The back face is uniformly coated with a metallisation layer (M1) in contact with the portions of the wafer. The thyristor is produced in lateral form, the isolation wall being in electrical contact with a control region of the same conductivity type as the thyristor and the logic portion includes a vertical component (20) with a main contact corresponding to the back face metallisation.

公开(公告)号：DE69715109T2

公开(公告)日：2003-04-30

申请号：DE69715109

申请日：1997-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： PEZZANI ROBERT

IPC: H01L21/332 ,  H01L29/74 ,  H01L29/747 ,  H03K17/72

Abstract: In a triac array, each triac comprises (a) a first conductivity type semiconductor substrate (1) bearing a second conductivity type layer (2) on its back face and having a second conductivity type deep diffusion (7) connecting the layer (2) to the front face; (b) second conductivity type first and second wells (4, 5) located at the front face side, the first well (4) containing a first conductivity type first region (3); (c) a first conductivity type second region (6) at the back face side and facing the second well (5); (d) a second conductivity type third well (10) containing a first conductivity type third region (11) and located at the front face side; (e) a back face metallisation (M1) corresponding to a first main electrode (A1); (f) a front face metallisation (M2) covering the top surface of the first region (3) and the second well (5) and corresponding to a second main electrode (A2); (g) a third metallisation (M3) covering the third well (10) or the third region (11) and connected to a trigger terminal (G); and (h) a fourth metallisation (M4) connecting the non-covered third well (10) or third region (11) to the top surface of the deep diffusion (7).

公开(公告)号：DE69715109D1

公开(公告)日：2002-10-10

申请号：DE69715109

申请日：1997-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： PEZZANI ROBERT

IPC: H01L21/332 ,  H01L29/74 ,  H01L29/747 ,  H03K17/72

Abstract: In a triac array, each triac comprises (a) a first conductivity type semiconductor substrate (1) bearing a second conductivity type layer (2) on its back face and having a second conductivity type deep diffusion (7) connecting the layer (2) to the front face; (b) second conductivity type first and second wells (4, 5) located at the front face side, the first well (4) containing a first conductivity type first region (3); (c) a first conductivity type second region (6) at the back face side and facing the second well (5); (d) a second conductivity type third well (10) containing a first conductivity type third region (11) and located at the front face side; (e) a back face metallisation (M1) corresponding to a first main electrode (A1); (f) a front face metallisation (M2) covering the top surface of the first region (3) and the second well (5) and corresponding to a second main electrode (A2); (g) a third metallisation (M3) covering the third well (10) or the third region (11) and connected to a trigger terminal (G); and (h) a fourth metallisation (M4) connecting the non-covered third well (10) or third region (11) to the top surface of the deep diffusion (7).

公开(公告)号：FR2822229A1

公开(公告)日：2002-09-20

申请号：FR0103471

申请日：2001-03-14

Applicant: ST MICROELECTRONICS SA

Inventor： PEZZANI ROBERT

IPC: G01D5/241 ,  G06K9/00 ,  G01D5/24

Abstract: Capacitive micro-sensor is formed on a plate (19) and comprises a conducting detection zone (4) arranged on the forward face of the plate, a conducting path (21) crossing the plate and linking the detection zone to contacts (22, 23) on the rear face of the plate. The plate has a silicon substrate and the internal walls of the substrate and conducting path are oxidized. An Independent claim is made for a fingerprint detector that uses an assembly of inventive micro- sensors.

公开(公告)号：FR2818824A1

公开(公告)日：2002-06-28

申请号：FR0016837

申请日：2000-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： GUITTON FABRICE ,  PEZZANI ROBERT

IPC: H01F27/28 ,  H02M1/08 ,  H03K17/94

Abstract: The invention concerns a control circuit for controlling a power switch by means of a galvanic insulation transformer, the transformer being produced in the form of planar conductive windings on an insulating substrate (20) whereon are integrated passive components constituting a high frequency excitation oscillating circuit for a primary winding of the transformer, the transformer substrate being directly mounted on a wafer (24) whereon is mounted a circuit chip (40) integrating the power switch.

公开(公告)号：AT206246T

公开(公告)日：2001-10-15

申请号：AT95410150

申请日：1995-12-27

Applicant: ST MICROELECTRONICS SA

Inventor： PEZZANI ROBERT

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/822 ,  H01L21/8222 ,  H01L23/40 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H05K7/20

Abstract: Conventional vertical components can be formed directly in the n-substrate having rear face covered with metallisation (M) corresp. to a common electrode. One type of isolated component has an active layer of opposite conductivity type on the rear face and is isolated by relatively heavily doped walls (6) which are overlapped by the dielectric layer (7) between the active layer and the metallisation.