公开(公告)号：FR2794310A1

公开(公告)日：2000-12-01

申请号：FR9907019

申请日：1999-05-28

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO OLIVIER PHILIPPE ,  DUGAS CHRISTOPHE

IPC: H03L3/00 ,  H03L7/08 ,  H04B1/16 ,  H04B1/40 ,  H04Q7/20

公开(公告)号：ITVA20040006A1

公开(公告)日：2004-05-11

申请号：ITVA20040006

申请日：2004-02-11

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： SIRITO OLIVIER PHILIPPE

IPC: H03F1/30 ,  H03F1/36 ,  H03F3/45

公开(公告)号：FR2821443B1

公开(公告)日：2003-06-20

申请号：FR0102579

申请日：2001-02-26

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO OLIVIER PHILIPPE

IPC: G05F3/26

Abstract: A current source includes a current mirror and a core connected together between two supply terminals. The current mirror comprises a pilot transistor and first and second recopy transistors. The core comprises first and second transistors and a resistance. The first transistor and the first recopy transistor are connected together to form a first branch. The resistance and the second recopy transistor are connected together to form a second branch. The pilot transistor and the second transistor are connected together to form a third branch. These branches are connected between the two supply terminals. The first transistor is linked to the second branch between the resistance and the second recopy transistor. The second transistor is connected to the first branch between the first core transistor and the first recopy transistor.

公开(公告)号：FR2821443A1

公开(公告)日：2002-08-30

申请号：FR0102579

申请日：2001-02-26

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO OLIVIER PHILIPPE

IPC: G05F3/26

Abstract: A current source includes a current mirror and a core connected together between two supply terminals. The current mirror comprises a pilot transistor and first and second recopy transistors. The core comprises first and second transistors and a resistance. The first transistor and the first recopy transistor are connected together to form a first branch. The resistance and the second recopy transistor are connected together to form a second branch. The pilot transistor and the second transistor are connected together to form a third branch. These branches are connected between the two supply terminals. The first transistor is linked to the second branch between the resistance and the second recopy transistor. The second transistor is connected to the first branch between the first core transistor and the first recopy transistor.

公开(公告)号：FR2821442A1

公开(公告)日：2002-08-30

申请号：FR0102578

申请日：2001-02-26

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO OLIVIER PHILIPPE

IPC: G05F3/22 ,  G05F3/26 ,  G05F3/30

Abstract: The supply voltage is applied between first and second terminals (Vcc,Vee) and the output transistor (T7) is connected to the first terminal and the base of a driver transistor (T6) which is part of a current mirror (Mi) including copying transistors (T4,T5). A heart circuit (C1) comprises two cross connected transistors (T1,T2) and a third transistor (T3). The heart and current mirror circuits are connected to form three branches between the terminals.

公开(公告)号：FR2809834B1

公开(公告)日：2002-08-23

申请号：FR0006913

申请日：2000-05-30

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO OLIVIER PHILIPPE

IPC: G05F3/26 ,  G05F3/16 ,  H01L23/48

Abstract: A current source includes a master branch including a branch current fixing resistor, at least one slave branch, and a current mirror including a mirror transistor in each of the master and slave branches, respectively, to couple the branches. The current source may additionally include at least one of a first circuit for injecting in the current fixing resistor a current proportional to the master branch current and a second circuit for injecting in a degeneration resistor of the mirror transistor of the slave branch a current proportional to a current of the slave branch. The invention is particularly applicable to the manufacture of integrated circuits.

公开(公告)号：FR2792475A1

公开(公告)日：2000-10-20

申请号：FR9904994

申请日：1999-04-16

Applicant: ST MICROELECTRONICS SA

Inventor： SIRITO OLIVIER PHILIPPE

IPC: G06F7/02 ,  H03K5/22

Abstract: The comparator has a CMOS decoder delivering 2n CMOS signals each corresponding to a different product of each of the n bits of the first digital value. There are 2n AND gates in ECL or CML technology which are associated with each of the 2n CMOS signals, and are connected to implement an OR function of the 2n bits that each correspond to a different product of the n bits of the ECL digital value. There is also a mechanism for deactivating the AND gates associated with the CMOS zero signals.