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公开(公告)号：FR2782421B1
公开(公告)日：2000-09-15
申请号：FR9810308
申请日：1998-08-11
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
Abstract: A device for generating a high voltage includes a charge pump device that outputs a high voltage, an oscillator that supplies at least one clock signal to the charge pump device, and a regulation device. The regulation device generates a control signal to selectively stop the charge pump device based on the level of the high voltage output by the charge pump device. Additionally, the oscillator includes a shaping circuit for shaping the clock signal into a saw-tooth waveform. In a preferred embodiment, the oscillator supplies at least two clock signals to the charge pump device, and each of the clock signals has a saw-tooth waveform. A method for generating a high voltage in an integrated circuit is also provided. According to the method, at least one clock signal is generated, and the clock signal is shaped into a saw-tooth waveform. The shaped clock signal is used to generate a high voltage, and the generation of the high voltage is selectively stopped based on the level of the high voltage. In one preferred method, at least two clock signals are generated, and each of the generated clock signals is shaped in to a saw-tooth waveform.
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公开(公告)号：DE69606968T2
公开(公告)日：2000-07-13
申请号：DE69606968
申请日：1996-12-24
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
IPC: H02M3/07
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公开(公告)号：DE69509735T2
公开(公告)日：1999-10-28
申请号：DE69509735
申请日：1995-12-21
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
Abstract: The standard resistance (105) substantially independent of temp. variations is fed from a first current source (125) while a chain (110) of two or more resistances is fed from a second current source (130) served by the same positive voltage (VDD). The individual resistances in the chain are paralleled by switches (S(1)-S(N)) opened and closed by outputs from an N-bit counter (140) of logic states of the comparator (135) of the voltages (V1,V2) developed across the standard resistance and the chain. The latter's resistances are switched (shorted) out so that its aggregate resistance matches that of the standard.
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公开(公告)号：DE69602984T2
公开(公告)日：1999-10-14
申请号：DE69602984
申请日：1996-03-06
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
Abstract: The address determined by the structure of the memory (ADF) or (ADFM) may be taken as the last address in the memory. The user commences writing sensitive information into the memory (MM) at an address of his choice (ADP) stored in a register (RV) and protected by a monostable (FW). The user entry ends at the structurally determined address (ADF) which activates a sequencer (SEQ1), a curtain (FL) and transfers the chosen address (ADP) into a non volatile register (RNV) establishing partition. A comparator (COMP) checks that subsequent addresses do not lie in the protected zone and inhibits the write authorisation (WE) if they do.
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公开(公告)号：DE69509735D1
公开(公告)日：1999-06-24
申请号：DE69509735
申请日：1995-12-21
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
Abstract: The standard resistance (105) substantially independent of temp. variations is fed from a first current source (125) while a chain (110) of two or more resistances is fed from a second current source (130) served by the same positive voltage (VDD). The individual resistances in the chain are paralleled by switches (S(1)-S(N)) opened and closed by outputs from an N-bit counter (140) of logic states of the comparator (135) of the voltages (V1,V2) developed across the standard resistance and the chain. The latter's resistances are switched (shorted) out so that its aggregate resistance matches that of the standard.
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Patent Agency Ranking
公开(公告)号：DE602007005289D1
公开(公告)日：2010-04-29
申请号：DE602007005289
申请日：2007-01-15
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
IPC: H01L27/092
Abstract: The method involves detecting a latch-up condition in an integrated circuit (IC). The detection of the latch-up condition comprises detecting injection of positive current and negative current in a connection terminal of the circuit, and detecting an over-voltage appearing in a supply connection terminal (VDD) of the circuit. A parameter of a supply voltage (Vdd) of the integrated circuit is modified if the latch-up condition is detected. Independent claims are also included for the following: (1) a device for protecting an integrated circuit (2) an integrated circuit comprising a protective device (3) a device for detecting a latch-up condition in an integrated circuit.
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公开(公告)号：FR2872630A1
公开(公告)日：2006-01-06
申请号：FR0407309
申请日：2004-07-01
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
IPC: H01L21/8238 , H01L29/74 , H01L27/092
Abstract: Circuit intégré comprenant des zones dopées (3 à 8) réalisées dans un substrat (1, 2), formant une structure de thyristor parasite à deux transistors bipolaires parasites (T1, T2), le circuit intégré comprenant deux métallisations (16, 19) interconnectant chacune deux zones dopées (4, 5 ; 6, 7) respectives du circuit intégré, pour réduire des résistances de base (RN-, RP-) des deux transistors bipolaires, au moins l'une des métallisations (16, 19) prévues pour réduire les résistances de base (RN-, RP-) des deux transistors bipolaires, étant reliée à une métallisation d'alimentation (15, 18) du circuit intégré, exclusivement par l'intermédiaire du substrat (1, 2).
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公开(公告)号：DE69534291D1
公开(公告)日：2005-08-04
申请号：DE69534291
申请日：1995-01-23
Applicant: ST MICROELECTRONICS SA
Inventor： TAILLIET FRANCOIS
IPC: H01L27/02
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公开(公告)号：DE69428480T2
公开(公告)日：2002-05-08
申请号：DE69428480
申请日：1994-05-25
Applicant: ST MICROELECTRONICS SA
Inventor： FOURNEL RICHARD , TAILLIET FRANCOIS
IPC: H01L21/8234 , H01L27/07 , H01L27/088 , H03B5/20 , H03K3/0231 , H03K3/86 , H03B5/24
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公开(公告)号：FR2809246A1
公开(公告)日：2001-11-23
申请号：FR0006262
申请日：2000-05-17
Applicant: ST MICROELECTRONICS SA
Inventor： LA ROSA FRANCESCO , TAILLIET FRANCOIS
Abstract: The slope voltage generator (45) comprises an output transistor (51) of p-MOS type laid out so to receive on its source a voltage (Vpp) to be delivered gradually on its drain, where the drain is connected to the anodic pole of a capacitor (Cr). The cathodic pole of the capacitor (Cr) is connected to a low potential, the ground (GND), by the intermediary of a constant current generator (52), and connected electrically to the gate of output transistor (51) by the intermediary of a transistor (53) of n-MOS type. The transistor (53) has its source connected to the cathodic pole of capacitor (Cr), and its drain to the gate of output transistor (51). The transistor (53) receives on its gate a dc. voltage (Vcc) which is lower than the voltage (Vpp), and on its drain a current (I2) delivered by another constant current generator (54). Each constant current generator (52,54) delivers a current equal or proportional to a reference current (I2) traversing the reference stage (42). The first current generator (52) comprises a set of transistors (52-1, 52-2, ..., 52-n) connected in parallel and controlled by a reference voltage (Vref), and delivers a current (I1) which is a multiple of the current (I2) delivered by the second current generator (54). The reference stage (42) comprises a transistor (55) of p-MOS type connected as a diode, a transistor (56) of n-MOS type receiving on its gate the voltage (Vcc), and a transistor (57) of n-MOS type receiving on its gate the reference voltage (Vref), which is lower than the voltage (Vcc). The start-stop means include a transistor (58) for blocking the output transistor (51), and a transistor (59) for pulling the output (Vout) back to the ground. An electrically programmable and erasable memory comprises a voltage generator for the delivery of higher voltage (Vpp), typically 15-20 V, which is applied to the memory cells by the intermediary of a voltage slope generator of proposed type.
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