公开(公告)号：JP2000250816A

公开(公告)日：2000-09-14

申请号：JP19942698

申请日：1998-06-10

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G06F12/14 ,  G06F21/24 ,  G07F7/10

Abstract: PROBLEM TO BE SOLVED: To prevent the malfunction of an integrated circuit by activating a change in the response of the integrated circuit while using the ordinary instruction of the integrated circuit to be used for an application program, and detecting a scenario of that activation. SOLUTION: Another transmitter M3' connected parallel to a transistor M3 of a first arm is provided and a current Iref is let flow by the current mirror effect of a transistor M1. Then, that transistor M3' is connected to a ground and activated by a selecting transistor M5, a scenario of that activation is detected by the sequence of instructions received by an integrated circuit and according to that detected scenario, one response of the integrated circuit is changed. Thus, the integrated circuit can be programmed so as not to generate the malfunction and can be operated against illegal access.

公开(公告)号：DE60133987D1

公开(公告)日：2008-06-26

申请号：DE60133987

申请日：2001-12-18

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G11C16/32 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50

公开(公告)号：FR2872630B1

公开(公告)日：2006-12-01

申请号：FR0407309

申请日：2004-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/74

Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RN−, RP−) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN−, RP−) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).

公开(公告)号：FR2858725A1

公开(公告)日：2005-02-11

申请号：FR0309680

申请日：2003-08-06

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: H02M3/07

Abstract: A generator produces a high voltage from a power supply voltage. The generator includes an oscillator for producing a driving signal, and a charge pump for producing the high voltage from the power supply voltage based upon receiving the driving signal. The charge pump includes n series-connected voltage step-up stages including a first step-up stage receiving the power supply voltage and a last step-up stage producing the high voltage, at least one replacement step-up stage, and a switching circuit. The switching circuit replaces a damaged one of the n series-connected voltage step-up stages with the at least one replacement stage when a warning signal is received. A voltage regulator produces an activation signal for activating the oscillator if the high voltage is below a desired value. A detector produces the warning signal if the charge pump is defective.

公开(公告)号：FR2792761B1

公开(公告)日：2003-05-23

申请号：FR9905051

申请日：1999-04-21

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G11C16/30 ,  G11C16/06 ,  H02M3/07

Abstract: A device for the programming of cells of an electrically programmable non-volatile memory. The device comprising a first reference input for receiving an erase signal for erasing one or more memory cells in the non-volatile memory and a second reference input for receiving an programming signal for programming one or more memory cells in the non-volatile memory. A regulation circuit coupled to the first reference input and coupled to the second reference input for regulating the magnitude of an erasure signal and for regulating the magnitude of a programming signal so that an electric field of approximate equal absolute magnitude is created on the floating gate of one or more memory cells during an erase type operation and an programming type operation.

公开(公告)号：FR2818424B1

公开(公告)日：2003-02-28

申请号：FR0016703

申请日：2000-12-20

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/32 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G01R31/00 ,  G01R31/303

公开(公告)号：FR2826496A1

公开(公告)日：2002-12-27

申请号：FR0108347

申请日：2001-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS ,  LA ROSA FRANCESCO

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/22

Abstract: The memory circuit (20) of type EEPROM comprises the memory cells (CEi,j) each containing a floating-gate transistor (FGT) and an access transistor (AT) of type MOS, wherein the drain of the floating-gate transistor is connected to the access transistor, and circuits/blocks including a charge pump (PMP), a row decoder (RDEC1), a column decoder (CDEC) and a column latch (LCk) for applying during the erasing phase, the electric voltages (Vcg=Vpp, Vs=0) to the gate and to the source, respectively, of the floating-gate transistors. The row decoder (RDEC1) has another output connected to an access transistor line (ATLi) for applying a determined electric signal (Vat) to the gates of the access transistors of the memory cells to be erased; the voltage value (Vat=0) is different from the programming voltage (Vpp) and is actually the difference between a low or null potential and the source voltage (Vs=0). The source voltage (Vs) is null during the erasing phase. The electric signal voltage (Vat) is null or floating during the erasing phase. The memory cells are arranged according to the word lines (WLi). The row decoder (RDEC1) delivers the word-line selection signal (Vw1) during the erasing phase, the programming and the reading of the memory cell. The row decoder (RDEC1) contains a logic circuit to prevent the application of the word-line selection signal (Vw1) to the process transistor line (ATLi) during the erasing phase, and for applying the electric signal (Vat=0) instead of the word-line selection signal. The memory comprises a control gate transistor (CGTk) for controlling the gates of the floating-gate transistors (FGT) in each row, and circuits/blocks including a current control circuit (ICC) and programming latches (LPIj) for limiting the programming current through the bit line during the programming phase. A supply voltage (Vcc), which is lower than the programming voltage (Vpp), is applied to the gate of the control gate transistor (CGTk) during the programming phase. An Independent claim is also included for method for the erasing and the programming of a memory cell.

公开(公告)号：FR2803100B1

公开(公告)日：2002-12-06

申请号：FR9916604

申请日：1999-12-28

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: H01L27/02 ,  H01L23/60 ,  H01L21/8229

Abstract: The protection device for an interconnection line of an integrated circuit includes a charge flow-off device connected between the interconnection line to be protected and the substrate of the integrated circuit. The protection device also includes a dummy interconnection line ANT to activate the flow-off device. The protection device is active throughout the manufacture of the integrated circuit.

公开(公告)号：DE69800343T2

公开(公告)日：2001-02-22

申请号：DE69800343

申请日：1998-06-09

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G06F12/14 ,  G06F21/24 ,  G07F7/10 ,  G07F7/12 ,  G06K19/073

公开(公告)号：ES2150408T3

公开(公告)日：2000-12-01

申请号：ES88402730

申请日：1988-10-28

Applicant: ST MICROELECTRONICS SA

Inventor： KOWALSKI JACEK ,  TAILLIET FRANCOIS

IPC: H01L23/60 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/866 ,  H01L29/72

Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.