公开(公告)号：DE69923539T2

公开(公告)日：2006-02-16

申请号：DE69923539

申请日：1999-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： WOJCIESZAK LAURENT ,  FERRANTE SONIA

IPC: G06F9/38 ,  G11C8/00 ,  G11C8/16

公开(公告)号：GB2365546B

公开(公告)日：2004-02-18

申请号：GB9930586

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  SENAME ISABELLE

IPC: G06F11/36

Abstract: A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be "killed" later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.

公开(公告)号：GB2366006A

公开(公告)日：2002-02-27

申请号：GB9930587

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  SENAME ISABELLE

IPC: G06F9/38 ,  G06F11/36

Abstract: A computer system where step-by-step execution of an instruction sequence is implemented, each instruction including a guard value. The guard value determines whether the instruction is executed. If after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is non-committed the next instruction in the sequence is executed. The system includes a pipelined execution unit and an emulation unit. The application discloses both a system and a method of execution. Also disclosed is a computer system where a decode unit is set in a stall state, either by reading stall attributes associated with debug instructions or in response to a stall command from an on-chip emulation unit. A method is also described.

公开(公告)号：GB2365546A

公开(公告)日：2002-02-20

申请号：GB9930586

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  SENAME ISABELLE

IPC: G06F11/36

Abstract: A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be "killed" later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.