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    Memory cell with three states, two programmable and one non-programmed state, comprises pre-read stages and programming stages with resistors of polycrystalline silicon
    12.
    发明专利
    Memory cell with three states, two programmable and one non-programmed state, comprises pre-read stages and programming stages with resistors of polycrystalline silicon 未知

    公开(公告)号：FR2846776A1

    公开(公告)日：2004-05-07

    申请号：FR0213615

    申请日：2002-10-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART SYLVIE ,  WUIDART LUC

    IPC: G11C17/00 ,  G11C11/56 ,  G11C17/14 ,  G11C17/18 ,  H01L27/10 ,  G11C17/08

    Abstract: The memory cell (1) comprises at least one, in particular two branches (2,3) connected between two terminals (4,5) where the read voltage (Vr) is applied; each branch comprises two stages connected in series, that is a pre-read stage (6,7) each with two switchable resistors (Rg1,Rg2;Rg3,Rg4) connected in parallel, and a programming stage (8,9) containing a programmable resistor (Rp1,Rp2) of polycrystalline silicon, where the programmable resistors terminals (14,15) are accessible to a proper programming circuit to implement an irreversible decrease of each programmable resistance. The decrease (delta)Rp of the value of the programmable resistance (Rp1,Rp2) is predetermined and chosen to be greater than the difference (delta)Rg between two resistances (Rg1,Rg2;Rg3,Rg4) in the pair of each pre-read stage (6,7). The memory cell also comprises interrupters (K10,K11) for isolating the pre-read stages (6,7) from the programming stages (8,9). The programming stages comprise switches (K14,K15) for aplying the programming voltage (Vp) which is higher than the read voltage (Vr) to the terminals of the programmable resistors (Rp1,Rp2). The reading of the cell state is effected in two successive steps in the course of which the switchable resistors (Rg1,Rg2,Rg3,Rg4) of the pre-read stages are alternatingly selected. Each programmable resistor (Rp1,Rp2) is connected to the lower supply voltage terminal, in particular the ground (5) by a transistor (MN1,MN2) connected as a bistable with the transistor of the other branch. The switchable resistors (Rg1,Rg2;Rg3,Rg4) of the two branches (2,3) are simultaneously controlled so that the values of the selected resistances in each branch are inverted. The irreversible decrease (delta) Rp of the programmable resistances is greater than the difference (E) of the nominal values of the programmable resistances in the non-programmed state. In a variant of the memory cell, the terminal of the programmable resistor is the read terminal which is connectable to the first input of an amplifier whose second input is connected to a reference potential which is chosen at a level intermediate between the voltage levels at the read terminal in the two read phases when the programmable resistance is in the non-programmed state. A method (claimed) for reading the memory cell (claimed) consists in effecting two successive read steps in the course of which the switchable resistances of the pre-read stage are selected.

    16.
    发明专利
    未知

    公开(公告)号：DE602006003886D1

    公开(公告)日：2009-01-08

    申请号：DE602006003886

    申请日：2006-03-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART SYLVIE

    IPC: G11C7/24 ,  G11C16/22

    Abstract: A memory is secured against an error injection during the reading of a datum. The memory includes: means for reading a reference datum in the memory during a phase of reading a datum stored in the memory; means for comparing the reference datum read with an expected value; and means for generating an error signal if the datum read is different from the expected value. Application is provided particularly but not exclusively to the protection of memories integrated into smart cards.

    LECTURE DE L'ETAT D'UN ELEMENT DE MEMORISATION NON VOLATILE
    17.
    发明专利
    LECTURE DE L'ETAT D'UN ELEMENT DE MEMORISATION NON VOLATILE 未知

    公开(公告)号：FR2875329A1

    公开(公告)日：2006-03-17

    申请号：FR0452058

    申请日：2004-09-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART SYLVIE

    IPC: G11C7/10 ,  G11C7/06

    Abstract: L'invention concerne un procédé de lecture de l'état d'un élément de mémorisation non volatile (4), consistant à conditionner la fréquence d'un premier oscillateur (1) à l'état de cet élément, et à comparer la fréquence du premier oscillateur à la fréquence prédéterminée d'un deuxième oscillateur (2), choisie pour être comprise entre deux valeurs possibles de fréquence du premier oscillateur selon l'état de l'élément de mémorisation

    18.
    发明专利
    未知

    公开(公告)号：FR2829265A1

    公开(公告)日：2003-03-07

    申请号：FR0111435

    申请日：2001-09-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART SYLVIE ,  WUIDART LUC ,  BARDOUILLET MICHEL ,  BALTHAZAR PIERRE

    IPC: G06F12/14 ,  G01K7/00 ,  G06F13/42 ,  G06F21/06 ,  G06K19/073 ,  H01L21/822 ,  H01L27/04

    Abstract: Method for detection of variations of an evironmental parameter (V,T) in an integrated circuit (1): (a) evaluate a propagation delay for retarding parts (21) sensitive to variations parameters environment, and; compare the delay current with respect to a reference value (REF). The measured delay current is compared to two predetermined minimum and maximum levels or a unique reference value defining a authorized operating range for the integrated circuit. The value from programmable retarder is determined as a function of the difference between the current value and reference value. The range of possible variation being predetermined.

    19.
    发明专利
    未知

    公开(公告)号：DE69622071D1

    公开(公告)日：2002-08-08

    申请号：DE69622071

    申请日：1996-03-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART SYLVIE

    IPC: G11C11/413 ,  G06F11/16 ,  G06F21/00 ,  G11C5/00 ,  G11C29/00 ,  G11C29/12 ,  G11C29/34 ,  G06F1/00

    Abstract: The information coherence detector operates with a memory circuit (14) having an element (15) comprising a capacitance (16) whose first terminal is connected to a logical voltage (Vss) and whose second terminal is connected to a node (X0) within a looping circuit having inverters (17,18) in series. The detector comprises an indicator circuit containing complementary information, and a circuit monitoring the complementarity of the information in order to detect and perturbation phenomena causing incoherence in the information. The indicator circuit includes at least two elements of this type (19,20), the complementarity is determined by placing a load transistor between the node in the looping circuit and a first or second logical voltage.

    20.
    发明专利
    未知

    公开(公告)号：FR2818847A1

    公开(公告)日：2002-06-28

    申请号：FR0017002

    申请日：2000-12-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART SYLVIE

    IPC: G06F7/00 ,  G06F21/72 ,  G06F21/75 ,  G07F7/10 ,  H04L9/32

    Abstract: The invention concerns a method for jamming the operating conditions of a logic circuit (30) designed to execute a specific logic function. The invention is characterised in that it consists in: providing in the logic circuit logic gates (10) and/or transistors adapted to execute the logic function at least in two different ways, the way in which the logic function is executed being determined by the value of a function selecting signal (R) applied to the logic circuit; then in applying to the logic circuit a random function selecting signal (R), and in refreshing the function selecting signal at specific times, so as to jam the operating conditions of the logic circuit. Thus, for identical data applied to the logic circuit input and different values of function selecting signal, the polarities of certain internal nodes of the logic circuit and/or the logic circuit power consumption are not identical.

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