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公开(公告)号:IT1268473B1
公开(公告)日:1997-03-04
申请号:ITVA930023
申请日:1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor: FAGNANI MAURO , FERRARIO BRUNO , SANDRI PAOLO
Abstract: A circuit for regulating the time of charging of the output node of an amplifier at start up, commonly comprising an external soft-start capacitor charged by a current delivered by a pull-up transistor (QG19) of a push-pull output stage of the amplifier, through a decoupling diode (QG23) that is functionally connected between the output node of the amplifier and an armature of the external soft-start capacitor, is provided with a current mirror feed back circuit capable of mirroring a current function of the charge current of the external soft-start capacitor on the driving node of the pull-up transistor (QG19) of the output stage of the amplifier. The regulating circuit permits to use an external capacitance of extremely small size and upon the reaching of a fully charged condition by the external capacitor, the control circuit self-isolates and does not influence in any way the normal operation of the amplifier.
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公开(公告)号:ITVA930023D0
公开(公告)日:1993-10-22
申请号:ITVA930023
申请日:1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor: FAGNANI MAURO , FERRARIO BRUNO , SANDRI PAOLO
Abstract: A circuit for regulating the time of charging of the output node of an amplifier at start up, commonly comprising an external soft-start capacitor charged by a current delivered by a pull-up transistor (QG19) of a push-pull output stage of the amplifier, through a decoupling diode (QG23) that is functionally connected between the output node of the amplifier and an armature of the external soft-start capacitor, is provided with a current mirror feed back circuit capable of mirroring a current function of the charge current of the external soft-start capacitor on the driving node of the pull-up transistor (QG19) of the output stage of the amplifier. The regulating circuit permits to use an external capacitance of extremely small size and upon the reaching of a fully charged condition by the external capacitor, the control circuit self-isolates and does not influence in any way the normal operation of the amplifier.
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公开(公告)号:IT1313865B1
公开(公告)日:2002-09-24
申请号:ITMI992361
申请日:1999-11-11
Applicant: ST MICROELECTRONICS SRL
Inventor: CAMERA ALESSANDRO , BELLOMO IGNAZIO , SANDRI PAOLO
IPC: G11C29/50
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公开(公告)号:ITMI992361D0
公开(公告)日:1999-11-11
申请号:ITMI992361
申请日:1999-11-11
Applicant: ST MICROELECTRONICS SRL
Inventor: CAMERA ALESSANDRO , BELLOMO IGNAZIO , SANDRI PAOLO
IPC: G11C29/50
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公开(公告)号:DE69413638T2
公开(公告)日:1999-02-25
申请号:DE69413638
申请日:1994-07-25
Applicant: ST MICROELECTRONICS SRL
Inventor: FAGNANI MAURO , FERRARIO BRUNO , SANDRI PAOLO
Abstract: A circuit for regulating the time of charging of the output node of an amplifier at start up, commonly comprising an external soft-start capacitor charged by a current delivered by a pull-up transistor (QG19) of a push-pull output stage of the amplifier, through a decoupling diode (QG23) that is functionally connected between the output node of the amplifier and an armature of the external soft-start capacitor, is provided with a current mirror feed back circuit capable of mirroring a current function of the charge current of the external soft-start capacitor on the driving node of the pull-up transistor (QG19) of the output stage of the amplifier. The regulating circuit permits to use an external capacitance of extremely small size and upon the reaching of a fully charged condition by the external capacitor, the control circuit self-isolates and does not influence in any way the normal operation of the amplifier.
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公开(公告)号:ITVA930022A1
公开(公告)日:1995-04-24
申请号:ITVA930022
申请日:1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor: BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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公开(公告)号:ITVA930022D0
公开(公告)日:1993-10-22
申请号:ITVA930022
申请日:1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor: BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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