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公开(公告)号：JPH07177732A
公开(公告)日：1995-07-14
申请号：JP28424194
申请日：1994-10-24
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: PURPOSE: To optimize the conversion efficiency of a converter which operates on low load level, without complicating a circuit by controlling first and second control loops, according to the condition of load level. CONSTITUTION: When a current duty cycle which is expressed by T0 NL0 GIc falls below a reference duty cycle, a circuit block T0 Nc0 NTR0 L disables the use of an error amplifier and a PWM comparator, whose output signals continuously constitute a PWM control network and enables the use of a hysteresis comparator CMS, whose output signal constitutes a hysteresis control network. On the other hand, when load condition is raised and a time interval TOFF falls under a preliminarily set value, a TOFF block generates a set signal whose output signal changes the condition and enables the use of the PWM control network, and disables the use of the hysteresis control network.
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公开(公告)号：JPH07183734A
公开(公告)日：1995-07-21
申请号：JP28424294
申请日：1994-10-24
Applicant: ST MICROELECTRONICS SRL
Inventor： FAGNANI MAURO , FERRARIO BRUNO , SANDRI PAOLO
Abstract: PURPOSE: To restrict the output voltage of amplifier by using an external soft start capacitor in small size while maintaining all the charging currents of external soft start capacitance in the order of microampere. CONSTITUTION: A current flowing through a charging diode QG 23 in the mirror circuit of TrQG 23 and 24 is mirrored by the TrQG 24. Through the mirror of Tr pair GQ 21 and 22 complementary for this mirror circuit, a current made proportional to the charging current flowing through the diode QG 23 and decreased suitably by using a suitable mirror ratio is inputted to the base of an output TrQG 19. The partial current mirrored by the base node of TrQG 19 is balanced partially with a charging current generated at a bypass oscillator MG 2. The current balance is achieved by a control loop, and all the charging currents of external soft start capacitor connected to a correspondent dedicated SS pin is maintained within the maximum value in order of 10 μA. Therefore, the voltage of output voltage COMP can be let rise gradually.
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公开(公告)号：US6424557B2
公开(公告)日：2002-07-23
申请号：US72857100
申请日：2000-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMERA ALESSANDRO , SANDRI PAOLO , BELLOMO IGNAZIO , MARINO FILIPPO
CPC classification number: H01L22/22
Abstract: An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and a memory for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.
Abstract translation: 集成装置包括至少一个电路元件和多个修整元件，其可以选择性地连接到至少一个电路元件，以便实现至少一个电路元件的特性参数的预定公差; 该集成装置包括多个电子开关，每个电子开关可以在第一状态和第二状态之间切换，在第一状态和第二状态之间，分别激活和去激活对应的修剪元件，以及用于存储状态指示的存储器 并且根据所存储的指示将每个电子开关操作在第一状态或第二状态。
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公开(公告)号：DE69431205D1
公开(公告)日：2002-09-26
申请号：DE69431205
申请日：1994-10-27
Applicant: ST MICROELECTRONICS SRL
Inventor： SANDRI PAOLO , BORGHI MARIA ROSA , RIGAZIO LUCA
Abstract: Switching losses in a DC-to-DC converter idling in a pulse-skipping mode are reduced by inhibiting any intervening turn-off command by a PWM control loop of the converter for as long as the current through the inductor of the converter remains below a minimum threshold value set by a dedicated comparator. The method is implemented by employing a comparator with a certain hysteresis and by logically masking the switching to a logic "0" of a high frequency clock (switching) signal of the converter for the entire period of time the current in the inductor remains below the minimum threshold.
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公开(公告)号：IT1268472B1
公开(公告)日：1997-03-04
申请号：ITVA930022
申请日：1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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Patent Agency Ranking
公开(公告)号：DE69421148D1
公开(公告)日：1999-11-18
申请号：DE69421148
申请日：1994-07-25
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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公开(公告)号：ITVA930023A1
公开(公告)日：1995-04-24
申请号：ITVA930023
申请日：1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： FAGNANI MAURO , FERRARIO BRUNO , SANDRI PAOLO
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公开(公告)号：DE69421148T2
公开(公告)日：2000-01-27
申请号：DE69421148
申请日：1994-07-25
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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公开(公告)号：DE69413638D1
公开(公告)日：1998-11-05
申请号：DE69413638
申请日：1994-07-25
Applicant: ST MICROELECTRONICS SRL
Inventor： FAGNANI MAURO , FERRARIO BRUNO , SANDRI PAOLO
Abstract: A circuit for regulating the time of charging of the output node of an amplifier at start up, commonly comprising an external soft-start capacitor charged by a current delivered by a pull-up transistor (QG19) of a push-pull output stage of the amplifier, through a decoupling diode (QG23) that is functionally connected between the output node of the amplifier and an armature of the external soft-start capacitor, is provided with a current mirror feed back circuit capable of mirroring a current function of the charge current of the external soft-start capacitor on the driving node of the pull-up transistor (QG19) of the output stage of the amplifier. The regulating circuit permits to use an external capacitance of extremely small size and upon the reaching of a fully charged condition by the external capacitor, the control circuit self-isolates and does not influence in any way the normal operation of the amplifier.
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公开(公告)号：ITMI992361A1
公开(公告)日：2001-05-11
申请号：ITMI992361
申请日：1999-11-11
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMERA ALESSANDRO , BELLOMO IGNAZIO , SANDRI PAOLO
IPC: G11C29/50
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