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公开(公告)号：JPH07177732A
公开(公告)日：1995-07-14
申请号：JP28424194
申请日：1994-10-24
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: PURPOSE: To optimize the conversion efficiency of a converter which operates on low load level, without complicating a circuit by controlling first and second control loops, according to the condition of load level. CONSTITUTION: When a current duty cycle which is expressed by T0 NL0 GIc falls below a reference duty cycle, a circuit block T0 Nc0 NTR0 L disables the use of an error amplifier and a PWM comparator, whose output signals continuously constitute a PWM control network and enables the use of a hysteresis comparator CMS, whose output signal constitutes a hysteresis control network. On the other hand, when load condition is raised and a time interval TOFF falls under a preliminarily set value, a TOFF block generates a set signal whose output signal changes the condition and enables the use of the PWM control network, and disables the use of the hysteresis control network.
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公开(公告)号：JPH07177731A
公开(公告)日：1995-07-14
申请号：JP28424394
申请日：1994-10-24
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , MENNITI PIETRO
Abstract: PURPOSE: To secure a discontinuous mode, while minimizing the number of leads by equipping a DC-to-DC converter with a comparator which generates an off signal, when it goes beyond a set value, a comparator which generates a switch off confirmation signal, and a means which masks the off signal. CONSTITUTION: A transistor(Tr)M1 is made conducting, and an inductor(ID)LEXT is charged, and the voltage VD is sensed with a comparator(CM)C2 . When the voltage VD reaches a voltage VREF2 , the output of the CM2 is switched from L to H, and the input of LOGIC is made H, and TrM1 is turned off. At this time, a voltage IDLEXT is discharged to a capacitor CEXT and load through a diode D. A current path, which is monitored with resistors R1 and R2 and a TrT2 and passes through the diode D, is sensed with CMC3, and it prevents the on of TrM1 , as long as the discharge current of the inductor is continued, confirming the L of the S input of FF. When the voltage monitored with CMC1 falls under a voltage VREF1 , the output of CMC1 becomes L, and TrM1 is turned on.
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公开(公告)号：DE69422138D1
公开(公告)日：2000-01-20
申请号：DE69422138
申请日：1994-08-05
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , MENNITI PIETRO
Abstract: A converter employs a comparator (C3) sensing the current through an output diode (D), for generating a confirmation signal of an OFF state of the switch (M1) until the discharge current of the inductor (L) toward the user circuit and the external filter capacitance (C) has become null, thus ensuring the operation in a discontinuous mode under any condition. A turn-off signal of the switch (M1) is provided by another comparator (C2) which, instead of the voltage on a sensing resistance connected in series with the switch, may sense the voltage across the switch (M1) itself. This latter embodiment is particularly suited in case of an output MOS transistor and the circuit comprises means for masking for a preset period of time the turn-off signal produced by said comparator (C2), in order to allow a predefined turn-on phase of the switch. Enabling of the turn-on of the switch (M1) is conventionally provided by a dedicated (third) comparator (C1) of the output voltage. The circuit does not require the use of an error amplifier, for the compensation of which special complex integratable circuits or alternatively access to the output node of the error amplifier through a dedicated pin may be needed.
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公开(公告)号：DE69421148D1
公开(公告)日：1999-11-18
申请号：DE69421148
申请日：1994-07-25
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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公开(公告)号：DE69431205D1
公开(公告)日：2002-09-26
申请号：DE69431205
申请日：1994-10-27
Applicant: ST MICROELECTRONICS SRL
Inventor： SANDRI PAOLO , BORGHI MARIA ROSA , RIGAZIO LUCA
Abstract: Switching losses in a DC-to-DC converter idling in a pulse-skipping mode are reduced by inhibiting any intervening turn-off command by a PWM control loop of the converter for as long as the current through the inductor of the converter remains below a minimum threshold value set by a dedicated comparator. The method is implemented by employing a comparator with a certain hysteresis and by logically masking the switching to a logic "0" of a high frequency clock (switching) signal of the converter for the entire period of time the current in the inductor remains below the minimum threshold.
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Patent Agency Ranking
公开(公告)号：IT1268472B1
公开(公告)日：1997-03-04
申请号：ITVA930022
申请日：1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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公开(公告)号：ITVA930024A1
公开(公告)日：1995-04-24
申请号：ITVA930024
申请日：1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , MENNITI PIETRO
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公开(公告)号：DE69422138T2
公开(公告)日：2000-04-20
申请号：DE69422138
申请日：1994-08-05
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , MENNITI PIETRO
Abstract: A converter employs a comparator (C3) sensing the current through an output diode (D), for generating a confirmation signal of an OFF state of the switch (M1) until the discharge current of the inductor (L) toward the user circuit and the external filter capacitance (C) has become null, thus ensuring the operation in a discontinuous mode under any condition. A turn-off signal of the switch (M1) is provided by another comparator (C2) which, instead of the voltage on a sensing resistance connected in series with the switch, may sense the voltage across the switch (M1) itself. This latter embodiment is particularly suited in case of an output MOS transistor and the circuit comprises means for masking for a preset period of time the turn-off signal produced by said comparator (C2), in order to allow a predefined turn-on phase of the switch. Enabling of the turn-on of the switch (M1) is conventionally provided by a dedicated (third) comparator (C1) of the output voltage. The circuit does not require the use of an error amplifier, for the compensation of which special complex integratable circuits or alternatively access to the output node of the error amplifier through a dedicated pin may be needed.
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公开(公告)号：DE69421148T2
公开(公告)日：2000-01-27
申请号：DE69421148
申请日：1994-07-25
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , SANDRI PAOLO
Abstract: A buck converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit as referred to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
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公开(公告)号：IT1268474B1
公开(公告)日：1997-03-04
申请号：ITVA930024
申请日：1993-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： BORGHI MARIA ROSA , MENNITI PIETRO
Abstract: A converter employs a comparator (C3) sensing the current through an output diode (D), for generating a confirmation signal of an OFF state of the switch (M1) until the discharge current of the inductor (L) toward the user circuit and the external filter capacitance (C) has become null, thus ensuring the operation in a discontinuous mode under any condition. A turn-off signal of the switch (M1) is provided by another comparator (C2) which, instead of the voltage on a sensing resistance connected in series with the switch, may sense the voltage across the switch (M1) itself. This latter embodiment is particularly suited in case of an output MOS transistor and the circuit comprises means for masking for a preset period of time the turn-off signal produced by said comparator (C2), in order to allow a predefined turn-on phase of the switch. Enabling of the turn-on of the switch (M1) is conventionally provided by a dedicated (third) comparator (C1) of the output voltage. The circuit does not require the use of an error amplifier, for the compensation of which special complex integratable circuits or alternatively access to the output node of the error amplifier through a dedicated pin may be needed.
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