公开(公告)号：US11915989B2

公开(公告)日：2024-02-27

申请号：US17573339

申请日：2022-01-11

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Graziosi ,  Aurora Sanna ,  Riccardo Villa

IPC: H01L23/31 ,  H01Q1/22 ,  H01L23/538 ,  H01L23/66

CPC classification number: H01L23/3114 ,  H01L23/5389 ,  H01L23/66 ,  H01Q1/2283 ,  H01L2223/6677

Abstract: An antenna-in-package semiconductor device includes a semiconductor chip coupled to a planar substrate. An encapsulation body encapsulates the semiconductor chip. The encapsulation body includes a through cavity extending to the planar substrate. A rectilinear wire antenna is mounted within the through cavity and extends, for instance from the planar substrate, along an axis that is transverse to a surface of the planar substrate to which the semiconductor chip is coupled. The rectilinear wire antenna is electrically coupled to the semiconductor chip. An insulating material fills the cavity to encapsulated the rectilinear wire antenna.

公开(公告)号：US11705388B2

公开(公告)日：2023-07-18

申请号：US17108694

申请日：2020-12-01

Applicant: STMicroelectronics S.r.l.

Inventor： Cristina Somma ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L27/02 ,  H01L23/538 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/14 ,  H01L23/50 ,  H01L23/5386 ,  H01L27/0207 ,  H01L2924/15321

Abstract: A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.

公开(公告)号：US11521861B2

公开(公告)日：2022-12-06

申请号：US16994049

申请日：2020-08-14

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Derai ,  Giovanni Graziosi

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495

Abstract: Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.

公开(公告)号：US09428380B2

公开(公告)日：2016-08-30

申请号：US14686540

申请日：2015-04-14

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Alex Gritti

IPC: H01L23/552 ,  B81B7/00 ,  H04R19/04 ,  H04R31/00 ,  H05K9/00 ,  H04R1/02 ,  H04R1/04 ,  H04R19/00

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L2224/48091 ,  H01L2224/48137 ,  H04R1/021 ,  H04R1/04 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/029 ,  H05K9/0009 ,  H01L2924/00014

Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.

公开(公告)号：US08854830B2

公开(公告)日：2014-10-07

申请号：US13779592

申请日：2013-02-27

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni Ziglioli ,  Giovanni Graziosi ,  Mario Francesco Cortese

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10 ,  H05K1/02 ,  H01L23/498 ,  B81B7/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H05K1/0271 ,  B81B7/0048 ,  B81B2207/07 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract translation: 一种适用于支撑损伤敏感器件的半导体封装衬底，包括具有第一和相对表面的衬底芯; 覆盖封装衬底芯的第一和相对表面的至少一对金属层，其限定第一和相对的金属层组，所述层组中的至少一个包括至少一个金属支撑区; 一对焊接掩模层，覆盖至少一对金属层的最外层金属层; 和多条路线; 其中所述至少一个金属支撑区域被形成为使得其位于所述损伤敏感装置的所述基部的至少一侧的下方，并且占据所述损伤敏感装置下方的所述区域的大部分，所述损伤敏感装置没有所述 路线; 还描述了制造这种基板的方法。

公开(公告)号：US20130170166A1

公开(公告)日：2013-07-04

申请号：US13779592

申请日：2013-02-27

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni Ziglioli ,  Giovanni Graziosi ,  Mario Francesco Cortese

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  B81B7/0048 ,  B81B2207/07 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract translation: 一种适用于支撑损伤敏感器件的半导体封装衬底，包括具有第一和相对表面的衬底芯; 覆盖封装衬底芯的第一和相对表面的至少一对金属层，其限定第一和相对的金属层组，所述层组中的至少一个包括至少一个金属支撑区; 一对焊接掩模层，覆盖至少一对金属层的最外层金属层; 和多条路线; 其中所述至少一个金属支撑区域被形成为使得其位于所述损伤敏感装置的所述基部的至少一侧的下方，并且占据所述损伤敏感装置下方的所述区域的大部分，所述损伤敏感装置没有所述 路线; 还描述了制造这种基板的方法。

公开(公告)号：US11764134B2

公开(公告)日：2023-09-19

申请号：US16745043

申请日：2020-01-16

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Arrigoni ,  Giovanni Graziosi ,  Aurora Sanna

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/4952 ,  H01L23/49503

Abstract: A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.

公开(公告)号：US11626355B2

公开(公告)日：2023-04-11

申请号：US17470269

申请日：2021-09-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Michele Derai

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

公开(公告)号：US10593614B2

公开(公告)日：2020-03-17

申请号：US16398022

申请日：2019-04-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L49/02

Abstract: In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.

公开(公告)号：US20150364409A1

公开(公告)日：2015-12-17

申请号：US14733209

申请日：2015-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L21/52 ,  H01L23/367

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/52 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/18162

Abstract: An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

Abstract translation: 电子装置包括集成在模具上的电路，其具有前表面和后表面，在前表面上具有模具端子。 模具嵌入包括具有前表面和后表面的导热材料的基底的包装和通孔中。 模具在通孔中沉没。 第一绝缘材料层用模具端子的第一窗口覆盖模具前表面和封装前表面。 封装端子和封装导轨布置在第一绝缘层上。 第二绝缘材料层覆盖第一绝缘层和封装轨道，其具有用于访问封装端子的第二窗口。