公开(公告)号：US12300585B2

公开(公告)日：2025-05-13

申请号：US18369652

申请日：2023-09-18

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Arrigoni ,  Giovanni Graziosi ,  Aurora Sanna

IPC: H01L23/495 ,  H01L21/48

Abstract: Disclosed herein is a method for manufacturing a semiconductor product package. The method includes arranging a leadframe with one or more leads such that each lead has an inner end facing a portion of a die-pad, attaching a semiconductor chip to the die-pad, attaching a first electrically conductive mass to the die-pad such that it is aligned with the inner end of a lead protruding over the die-pad, attaching an electrical component to the first electrically conductive mass such that a longitudinal axis of the electrical component is arranged traverse to the die-pad, and coupling a second electrically conductive mass between a termination of the electrical component and the inner end of the lead.

公开(公告)号：US10211140B2

公开(公告)日：2019-02-19

申请号：US15616009

申请日：2017-06-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

公开(公告)号：US20170271254A1

公开(公告)日：2017-09-21

申请号：US15616009

申请日：2017-06-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/52 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/18162

Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

公开(公告)号：US20170250128A1

公开(公告)日：2017-08-31

申请号：US15282619

申请日：2016-09-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/495 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L28/60 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.

公开(公告)号：US09704794B2

公开(公告)日：2017-07-11

申请号：US14733209

申请日：2015-06-08

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/06 ,  H01L23/04 ,  H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/52 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/18162

Abstract: An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

公开(公告)号：US11152289B2

公开(公告)日：2021-10-19

申请号：US16406911

申请日：2019-05-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Michele Derai

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

公开(公告)号：US10283441B2

公开(公告)日：2019-05-07

申请号：US15282619

申请日：2016-09-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L49/02

Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.

公开(公告)号：US20150217993A1

公开(公告)日：2015-08-06

申请号：US14686540

申请日：2015-04-14

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Alex Gritti

IPC: B81B7/00 ,  H05K9/00

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L2224/48091 ,  H01L2224/48137 ,  H04R1/021 ,  H04R1/04 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/029 ,  H05K9/0009 ,  H01L2924/00014

Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.

Abstract translation: 一个或多个实施例涉及封装结构，包括：具有第一表面并且容纳至少一个导电焊盘的衬底，所述至少一个导电焊盘面向第一表面延伸并且被配置为在参考电压下电耦合到导通端子; 盖构件，其设置在离基板的第一表面一定距离处; 以及在基板和盖构件之间延伸的壳体壁。 衬底，盖构件和壳体壁限定空腔，其在封装结构内部并容纳导电垫。 此外，在腔内部还存在至少一个导电结构，其在盖构件和导电垫之间延伸并与之电接触，用于将盖构件电连接到导电端子。

公开(公告)号：US20130105952A1

公开(公告)日：2013-05-02

申请号：US13659753

申请日：2012-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Alex Gritti

IPC: H01L23/60 ,  H01L21/56

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L2224/48091 ,  H01L2224/48137 ,  H04R1/021 ,  H04R1/04 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/029 ,  H05K9/0009 ,  H01L2924/00014

Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.

公开(公告)号：US12068276B2

公开(公告)日：2024-08-20

申请号：US17344149

申请日：2021-06-10

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Graziosi ,  Michele Derai

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

CPC classification number: H01L24/82 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/49589 ,  H01L23/645 ,  H01L23/647 ,  H01L24/48 ,  H01L24/96 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/92 ,  H01L2224/24105 ,  H01L2224/24175 ,  H01L2224/24195 ,  H01L2224/48245 ,  H01L2224/48265 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/92244 ,  H01L2924/186

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.