公开(公告)号：EP1612802A2

公开(公告)日：2006-01-04

申请号：EP05254093.7

申请日：2005-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe

IPC: G11C11/16 ,  G11C11/41

CPC classification number: G11C14/0081 ,  G11C11/16

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.

Abstract translation: 磁性随机存取存储器元件由第一磁性隧道结和第二磁性隧道结构成。 锁存电路包括连接到第一磁隧道结的假节点和连接到第二磁隧道结的真节点。 一对互补位线与元件相关联地提供。 第一存取晶体管将位线中的错误位线与锁存电路的假节点互连，而第二存取晶体管将位线中的真实位线与锁存电路的真实节点互连。 存储元件相应地具有SRAM四晶体管（4T）双负载（2R）架构，其中与两个磁隧道结相关联的电阻提供两个负载电阻。

公开(公告)号：EP1736993B1

公开(公告)日：2010-08-11

申请号：EP06252950.8

申请日：2006-06-07

Applicant: STMicroelectronics, Inc.

Inventor： Dray, Cyrille ,  Barasinski, Sebastien ,  Lasseuguette, Jean ,  Frey, Christophe ,  Fournel, Richard

IPC: G11C11/16 ,  G11C7/18 ,  G11C8/14

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16

公开(公告)号：EP1369877B1

公开(公告)日：2010-08-11

申请号：EP03253553.6

申请日：2003-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe ,  LaLanne, Frederic ,  Lysinger, Mark A.

IPC: G11C15/04

CPC classification number: G11C15/04

公开(公告)号：EP1369877A2

公开(公告)日：2003-12-10

申请号：EP03253553.6

申请日：2003-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe ,  LaLanne, Frederic ,  Lysinger, Mark A.

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

Abstract translation: 公开了一种具有用于改善CAM单元和CAM阵列的半导体衬底区域利用率的晶体管的物理实现的内容可寻址存储器（CAM）单元。 CAM单元包括第一和第二存储器电路和比较电路。 六个晶体管的比较电路形成在两个有源区域上。 比较电路和由多晶硅区域形成的第一存储器电路之间的局部互连。 比较电路和由多晶硅和导电区域形成的第二存储器电路之间的局部互连。