公开(公告)号：EP1962290A1

公开(公告)日：2008-08-27

申请号：EP08151480.4

申请日：2008-02-15

Applicant: STMicroelectronics, Inc.

Inventor： Lysinger, Mark A. ,  McClure, David C. ,  Jacquet, François

IPC: G11C11/413 ,  G11C11/417 ,  G11C5/14

CPC classification number: G11C5/143 ,  G11C11/412 ,  G11C11/413

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.

Abstract translation: 电路包括具有高电压供应节点和低电压供应节点的存储单元。 提供功率复用电路以根据小区的当前操作模式来选择性地将第一组电压和第二组电压中的一个施加到小区的高电压和低电压供应节点。 如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。 相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。 第二组电压偏离第一组电压。 更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。 单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。 该阵列可以包括包括许多块或部分的整个存储器装置内的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。

公开(公告)号：EP1369877B1

公开(公告)日：2010-08-11

申请号：EP03253553.6

申请日：2003-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe ,  LaLanne, Frederic ,  Lysinger, Mark A.

IPC: G11C15/04

CPC classification number: G11C15/04

公开(公告)号：EP1369877A2

公开(公告)日：2003-12-10

申请号：EP03253553.6

申请日：2003-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe ,  LaLanne, Frederic ,  Lysinger, Mark A.

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

Abstract translation: 公开了一种具有用于改善CAM单元和CAM阵列的半导体衬底区域利用率的晶体管的物理实现的内容可寻址存储器（CAM）单元。 CAM单元包括第一和第二存储器电路和比较电路。 六个晶体管的比较电路形成在两个有源区域上。 比较电路和由多晶硅区域形成的第一存储器电路之间的局部互连。 比较电路和由多晶硅和导电区域形成的第二存储器电路之间的局部互连。

公开(公告)号：EP0459703B1

公开(公告)日：2000-08-16

申请号：EP91304677.7

申请日：1991-05-23

Applicant: STMicroelectronics, Inc.

Inventor： Lysinger, Mark A.

IPC: G06F17/30

CPC classification number: G06F17/30982 ,  G11C15/00

公开(公告)号：EP1959452B1

公开(公告)日：2011-10-26

申请号：EP08151479.6

申请日：2008-02-15

Applicant: STMicroelectronics, Inc.

Inventor： McClure, David C. ,  Lysinger, Mark A. ,  Zamanian, Mehdi ,  Jacquet, François ,  Roche, Philippe

IPC: G11C5/14 ,  G11C11/413 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/147 ,  G11C5/148 ,  G11C11/41 ,  G11C11/413 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

公开(公告)号：EP1959452A1

公开(公告)日：2008-08-20

申请号：EP08151479.6

申请日：2008-02-15

Applicant: STMicroelectronics, Inc.

Inventor： McClure, David C. ,  Lysinger, Mark A. ,  Zamanian, Mehdi ,  Jacquet, François ,  Roche, Philippe

IPC: G11C5/14 ,  G11C11/413 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/147 ,  G11C5/148 ,  G11C11/41 ,  G11C11/413 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are programmable to be selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract translation: 存储电路具有高电压和低电压电源节点。 根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。 如果处于主动读/写模式，则选择性地施加第一组电压。 相反，如果在备用无读/不写模式下，则选择性地施加第二组电压。 所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压由多个低失调电压中的选定的一个组成，并且所述第二组电压中的高电压小于所述第二组电压中的高电压 所述第一组电压通过多个高偏移电压中的所选择的一个。 偏移电压由可编程为有选择地活动的基于二极管的电路提供。 选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

公开(公告)号：EP1369877A3

公开(公告)日：2007-08-08

申请号：EP03253553.6

申请日：2003-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Frey, Christophe ,  LaLanne, Frederic ,  Lysinger, Mark A.

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.