公开(公告)号：EP0942373A1

公开(公告)日：1999-09-15

申请号：EP99301871.2

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00

CPC classification number: G06F11/3656

Abstract: An adapter device for assisting debugging of a microprocessor on a single integrated circuit chip, the integrated circuit chip comprising an on-chip CPU with a plurality of registers, a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU and an external communication port connected to the said bus on the integrated circuit chip, the communication port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device comprising a first communication unit for connection to the communication port with the first external format; a second communication unit for connection to an external computer device with a second external format having a higher latency than the first external format; a second memory local to the adapter device; and a processing unit local to the adapter device and operable: (a) in a first mode to translate between the first external format and the second external format to allow the external computer device to communicate directly with the communication port; (b) in a second mode to connect the second communication unit to the second memory to allow the external computer device to access the second memory; and (c) in a third mode to execute instructions stored in the second memory to transmit data via the first communication unit to the communication port.

Abstract translation: 一种用于辅助单个集成电路芯片上的微处理器调试的适配器装置，所述集成电路芯片包括具有多个寄存器的片上CPU，所述通信总线提供所述CPU与所述CPU之间的第一存储器的并行通信路径 CPU和连接到集成电路芯片上的所述总线的外部通信端口，所述通信端口具有内部并行信号格式的所述总线的内部连接以及与适配器单元的外部连接，所述第一外部格式不等于 所说的内部格式; 所述适配器装置包括用于以所述第一外部格式连接到所述通信端口的第一通信单元; 第二通信单元，用于连接到具有比第一外部格式更高的延迟的第二外部格式的外部计算机设备; 适配器设备本地的第二存储器; 以及适配器设备本地的处理单元，并且可操作：（a）以第一模式在第一外部格式和第二外部格式之间进行转换，以允许外部计算机设备与通信端口直接通信; （b）以第二模式将第二通信单元连接到第二存储器，以允许外部计算机设备访问第二存储器; 以及（c）在第三模式中执行存储在第二存储器中的指令，以经由第一通信单元向通信端口发送数据。

公开(公告)号：EP0942371A1

公开(公告)日：1999-09-15

申请号：EP99301834.0

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/3648

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device; the integrated circuit chip having: an on-chip CPU with a plurality of registers; a communication bus for addressing a plurality of devices assigned to a single memory address space of the CPU and providing a parallel communication path between the CPU and a first memory local to the CPU; an address memory for storing the assignment of addresses to the plurality of devices; and an external communication port connected to the communication bus, the port having an internal connection to the bus of an internal parallel signal format and an external connection to the external computer device of an external format less parallel than the said internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby the port may be addressed by execution of an instruction by the CPU; the external computer device having a second memory local to the external computer device, which is accessible by the CPU through the port; and the computer system having address diversion means for reconfiguring the memory address space of the CPU so as to assign to the port memory addresses of another one of the devices.

Abstract translation: 一种计算机系统，包括连接到外部计算机设备的单个集成电路芯片上的微处理器; 所述集成电路芯片具有：具有多个寄存器的片上CPU; 通信总线，用于寻址分配给CPU的单个存储器地址空间的多个设备，并且在CPU和CPU的本地的第一存储器之间提供并行通信路径; 地址存储器，用于存储对多个设备的地址分配; 以及连接到通信总线的外部通信端口，所述端口具有内部并行信号格式的总线的内部连接和外部计算机设备的外部连接，所述外部格式与所述内部格式不平行，所述端口形成 可以从其中取出指令的CPU的存储器地址空间的一部分，由此可以通过执行CPU的指令来寻址端口; 所述外部计算机设备具有外部计算机设备本地的第二存储器，所述第二存储器可由所述CPU通过所述端口访问; 并且所述计算机系统具有用于重新配置所述CPU的存储器地址空间的地址转移装置，以便分配给所述另一个设备的端口存储器地址。

公开(公告)号：EP0936537B1

公开(公告)日：2008-07-23

申请号：EP99300995.0

申请日：1999-02-11

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  Homewood, Marc Owen

IPC: G06F9/30 ,  G06F11/10

CPC classification number: G06F9/30018 ,  G06F11/10

公开(公告)号：EP1832996A1

公开(公告)日：2007-09-12

申请号：EP06251192.8

申请日：2006-03-06

Applicant: STMicroelectronics Limited

Inventor： Ryan, Stuart Andrew ,  Jones, Andrew Michael

IPC: G06F21/00

CPC classification number: G06F21/51

Abstract: A system is provided in which a first circuit is protected by security features provided by a second circuit. The first circuit comprises a processor which retrieves content from a memory. Initially, the contents of the memory are authenticated using security features of the second circuit to check that the processor is accessing authenticated content. To maintain security during use, the second circuit checks that the processor is accessing content from valid regions of the memory, being those that have been authenticated, and re-checks the authenticity of the content of the valid regions of memory. The combination of checking that the processor is accessing from valid regions of the memory and authenticating the content stored in the valid regions maximises the security of the system. If any of the checking or authentication steps fail then operation of the system is impaired. The first circuit is thus protected by security features provided by the second circuit.

Abstract translation: 提供了一种系统，其中由第二电路提供的安全特征来保护第一电路。 第一电路包括从存储器检索内容的处理器。 最初，使用第二电路的安全特征对存储器的内容进行认证，以检查处理器是否访问认证的内容。 为了在使用期间保持安全性，第二电路检查处理器是否从存储器的有效区域访问内容，即已经被认证的那些内容，并重新检查存储器的有效区域的内容的真实性。 检查处理器从存储器的有效区域进行访问并认证存储在有效区域中的内容的组合使得系统的安全性最大化。 如果任何检查或认证步骤失败，则系统的操作受损。 因此，第一电路由第二电路提供的安全特性来保护。

公开(公告)号：EP0945805B1

公开(公告)日：2007-01-03

申请号：EP99301960.3

申请日：1999-03-15

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael

IPC: G06F12/08

CPC classification number: G06F12/0837 ,  G06F12/0815

公开(公告)号：EP0942371B1

公开(公告)日：2003-05-21

申请号：EP99301834.0

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/3648

公开(公告)号：EP0840221B1

公开(公告)日：2002-09-18

申请号：EP97308488.2

申请日：1997-10-24

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  May, Michael David

IPC: G06F11/00

CPC classification number: G06F11/3648 ,  G06F11/1417

公开(公告)号：EP0953913A1

公开(公告)日：1999-11-03

申请号：EP99303255.6

申请日：1999-04-27

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  May, Michael David

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: An integrated circuit device (11) has an address and data path (15) interconnecting a CPU (12) with modules (14) the modules having event logic (8) to generate an event request packet having a destination address and the CPU decoding the packet to selectively respond to the request of the packet depending on the priority of the event.

Abstract translation: 集成电路装置（11）具有将CPU（12）与具有事件逻辑（8）的模块（14）互连的地址和数据路径（15），以生成具有目的地地址的事件请求分组，并且CPU对 分组以根据事件的优先级选择性地响应分组的请求。

公开(公告)号：EP0936537A1

公开(公告)日：1999-08-18

申请号：EP99300995.0

申请日：1999-02-11

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  Homewood, Marc Owen

IPC: G06F9/30 ,  G06F11/10

CPC classification number: G06F9/30018 ,  G06F11/10

Abstract: A cyclic redundancy check value is computed by iterating a loop in which the contents of an operand (50) having a first CRC value (51) and a data value (52) are shifted 1 bit to the end at which the CRC value is located, and a generator value (55) is exclusive-ORed into corresponding respective bits of the operand only if the bit shifted out of the operand by the shift was set, and this is repeated until a data byte has been displaced entirely and a modified cyclic redundancy check value (51) occupies the most significant bytes but now incorporates the original data byte in modified form.

Abstract translation: 通过迭代循环来计算循环冗余校验值，其中具有第一CRC值（51）和数据值（52）的操作数（50）的内容被移位1位到CRC值所在的结尾 ，并且只有当设置了从操作数移出移位位的位后，发生器值（55）才被异或运算到操作数的对应的各个位中，并重复该操作数，直到数据字节完全移位，并且修改了循环 冗余校验值（51）占用最高有效字节，但现在将原始数据字节并入修改后的形式。

公开(公告)号：EP1830268A1

公开(公告)日：2007-09-05

申请号：EP06251162.1

申请日：2006-03-03

Applicant: STMicroelectronics Limited

Inventor： Ryan, Stuart Andrew ,  Jones, Andrew Michael

IPC: G06F11/07 ,  G06F1/32

CPC classification number: G06F11/004 ,  Y10T307/911

Abstract: An integrated circuit comprises a plurality of units that may act as initiators and targets. At least some of the units being for a first purpose such as a cable modem function and others being for a second purpose such as television data processing. The units are connected together by a bus comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract translation: 集成电路包括可充当发起者和目标的多个单元。 至少一些单元是用于诸如电缆调制解调器功能的第一目的，而其他单元用于第二目的，例如电视数据处理。 这些单元通过包括多个节点的总线连接在一起。 节点之一是可配置的，使得从节点一侧的发起者单元到节点另一侧的目标单元的请求不发送到目标单元。 用于第一目的的单元被布置在与第二目的的节点的相对侧上，使得电路被有效地配置成两个单独的逻辑分区，用于电视数据处理的一个分区和用于电缆调制解调器功能的另一个分区。