公开(公告)号：EP0942374B1

公开(公告)日：2003-03-05

申请号：EP99301876.1

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/3664 ,  G06F11/261 ,  G06F11/3648

公开(公告)号：EP0942371B1

公开(公告)日：2003-05-21

申请号：EP99301834.0

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/3648

公开(公告)号：EP0942375B1

公开(公告)日：2003-05-21

申请号：EP99301877.9

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan

IPC: G06F11/00

CPC classification number: G06F11/3656 ,  G06F11/261

公开(公告)号：EP0840224B1

公开(公告)日：2002-09-18

申请号：EP97308518.6

申请日：1997-10-24

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  Edwards, David Alan ,  May,Michael David

IPC: G06F11/00

CPC classification number: G06F11/3648 ,  G06F9/4401 ,  G06F11/1417

公开(公告)号：EP0942375A1

公开(公告)日：1999-09-15

申请号：EP99301877.9

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan

IPC: G06F11/00

CPC classification number: G06F11/3656 ,  G06F11/261

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device via an adapter device; the integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU, the integrated circuit further comprising an external communication port connected to the said bus on the integrated circuit chip, the port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device being connected to the external communication port with the first external format and to the external computer with a second external format having a higher latency than the first external format, the adapter device having an interface for translating between the first external format and the second external format; the external computer device having a second memory local to the external computer device; and the second memory being accessible by the CPU through the port, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby the port may be addressed by execution of an instruction by the CPU.

Abstract translation: 一种计算机系统，其包括经由适配器装置连接到外部计算机设备的单个集成电路芯片上的微处理器; 具有片上CPU与寄存器的多个部分并加以提供所述CPU和第一存储器本地的CPU之间的并行通信路径的通信总线的集成电路芯片，所述集成电路进一步包括连接到上述总线的外部通信端口的 的集成电路芯片上，具有在内部连接的内部并行信号格式的到所述总线，并以第一外部格式比所述内部格式平行更少的适配器单元外部连接的端口; 适配器装置被连接到外部通信端口与所述第一外部格式和到外部计算机与具有比所述第一外部格式的更高的延迟的第二外部格式中，具有适配器设备接口用于第一外部格式和之间进行转换 第二外部格式; 具有第二存储器本地到外部计算机设备的外部计算机装置; 和第二存储器是由通过该端口的CPU访问，则口形成从哪个指令的CPU的存储器地址空间的一部分可以被提取，由此端口可以通过CPU的指令的执行来解决。

公开(公告)号：EP0942372A1

公开(公告)日：1999-09-15

申请号：EP99301847.2

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Farral, Glenn Ashley

IPC: G06F11/00

CPC classification number: G06F11/3648 ,  G06F11/348

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU which includes: a data processing unit for executing instructions; a data link connected between a memory and the data processing unit for passing instructions to the data processing unit; a watch register for storing an instruction comparison code; and a watch comparator coupled to the data link for comparing the instructions passed on the data link with the instruction comparison code and generating a comparison output signal in dependence on the result of the comparison.

Abstract translation: 一种计算机系统，包括具有片上CPU的单个集成电路芯片上的微处理器，其包括：用于执行指令的数据处理单元; 连接在存储器和数据处理单元之间的数据链路，用于将指令传递到数据处理单元; 用于存储指令比较代码的监视寄存器; 以及观察比较器，其耦合到数据链路，用于将在数据链路上传递的指令与指令比较代码进行比较，并根据比较结果生成比较输出信号。

公开(公告)号：EP0942373B1

公开(公告)日：2003-06-11

申请号：EP99301871.2

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00

CPC classification number: G06F11/3656

公开(公告)号：EP0942372B1

公开(公告)日：2003-05-14

申请号：EP99301847.2

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Farral, Glenn Ashley

IPC: G06F11/00

CPC classification number: G06F11/3648 ,  G06F11/348

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU which includes: a data processing unit for executing instructions; a data link connected between a memory and the data processing unit for passing instructions to the data processing unit; a watch register for storing an instruction comparison code; and a watch comparator coupled to the data link for comparing the instructions passed on the data link with the instruction comparison code and generating a comparison output signal in dependence on the result of the comparison.

公开(公告)号：EP0840222B1

公开(公告)日：2002-09-11

申请号：EP97308516.0

申请日：1997-10-24

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  Edwards, David Alan ,  May, Michael David

IPC: G06F11/00

CPC classification number: G06F11/3648 ,  G06F11/1417

公开(公告)号：EP0942374A1

公开(公告)日：1999-09-15

申请号：EP99301876.1

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/3664 ,  G06F11/261 ,  G06F11/3648

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device and at least one other device; the integrated circuit chip having: an on-chip CPU with a plurality of registers; a communication bus for providing a parallel communication path between the CPU and a first memory local to the CPU; and an external communication port connected to the communication bus, the port having an internal connection to the bus of an internal parallel signal format and an external connection to the external computer device of an external format less parallel than the said internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby: the port may be addressed by execution of an instruction by the CPU; and the external computer device may send to the integrated circuit chip an interrupt signal simulating an interrupt signal from the other device.

Abstract translation: 一种计算机系统，包括连接到外部计算机装置和至少一个其他设备在单个集成电路芯片上的微处理器; 具有集成电路芯片：一个片上CPU与寄存器的多元性; 用于提供所述CPU和第一本地存储器到CPU之间的并行通信路径的通信总线; 并连接到通信总线外部通信端口，具有一个内部并行信号格式的，并为外部格式的小于所述内部格式平行的外部计算机装置的外部连接的总线内部连接的端口，该端口形成 CPU的存储器地址空间从哪个指令可以被取出，由此的一部分：该端口可以通过由CPU的指令的执行来解决; 和外部计算机设备可以被发送到所述集成电路芯片中断信号模拟到从其他设备中断信号。