公开(公告)号：EP1052758A1

公开(公告)日：2000-11-15

申请号：EP99830285.5

申请日：1999-05-10

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Angelo ,  Capici, Salvatore ,  Marino, Filippo ,  Pulvirenti, Francesco

IPC: H02J7/00

CPC classification number: H02J7/0068 ,  H02M3/156 ,  H02M2001/0009

Abstract: The frequency translator (72) is usable in a switching DC-DC converter of the type operating as a voltage regulator and as a battery charger. The frequency translator (72) receives at inputs a division voltage (VFB) proportional to a present value of the output voltage (VOUT) of the DC-DC converter (70), a reference voltage (VREF) correlated to a nominal value of the output voltage (VOUT), and a limiting signal (VL) indicative of a normal operation or of current limitation operation of the DC-DC converter (70), and supplies at an output (72u) a bias current (IBIAS) which is supplied to an input of an oscillator (32) supplying at an output a comparison signal (VC) presenting a periodic pattern with a frequency which is correlated to the bias current (IBIAS). In particular, the frequency translator (72) operates in a way such as to regulate a frequency translation of the comparison signal (VC) as a function of the difference between the division voltage (VFB) and the reference voltage (VREF) only when the DC-DC converter (70) is operating in the current limitation condition.

Abstract translation: 频率变换器（72）是在作为电压调节器和作为电池充电器操作的类型的开关型DC-DC转换器使用。 频率转换器（72）接收在输入的分压电压（VFB）正比于相关的一个标称值的输出电压的DC-DC转换器（70），参考电压（VREF）的（VOUT）的当前值 输出电压（VOUT）和一个限制信号（VL）表示在上输出（72U）的偏置电流（I BIAS）正常操作或DC-DC转换器（70）的电流限制手术，和用品的所有被提供 对在以输出供给振荡器（32）的输入呈现的周期性图案的频率的所有其相关于偏置电流（I BIAS）的比较信号（VC）。 特别地，所述频率变换器（72）进行操作的方式：例如，以调节所述比较信号（VC）作为分割电压（VFB）和参考电压（VREF）之间的差的函数的一个频率转换只有当 DC-DC转换器（70）在电流限制的条件下操作。

公开(公告)号：EP1049229A1

公开(公告)日：2000-11-02

申请号：EP99830257.4

申请日：1999-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Salvatore ,  Pulvirenti, Francesco ,  Marino, Filippo

IPC: H02J7/00

CPC classification number: H02M3/156 ,  H02J7/0052 ,  H02J2007/0059 ,  Y10S323/901

Abstract: The DC-DC converter (1') comprises a current error amplifier (32') and a voltage error amplifier (42') connected in parallel to control the charging of the battery (18) and a gradual turning off circuit (44', 60) for turning off gradually the current error amplifier (32') in a battery charging end phase. In this way, the DC-DC converter is able to supply to the battery (18) a battery charging current that remains constant up until the battery full charge voltage is reached.

Abstract translation: 的DC-DC转换器（1“）包括电流误差放大器（32”）和一个电压误差放大器（42“）并联连接，以控制所述电池（18）和一个逐渐关断电路的充电（44” 60）一种用于在电池渐渐关闭电流误差放大器（32“）的充电结束阶段。 以这种方式，在DC-DC转换器能够提供给电池（18）的电池充电电流保持恒定，直到达到电池满充电电压。

公开(公告)号：EP2282406A2

公开(公告)日：2011-02-09

申请号：EP10169807.4

申请日：2010-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Giombanco, Salvatore ,  Grande, Michele ,  Lombardo, Giovanni ,  Tumminaro, Salvatore ,  Marino, Filippo

IPC: H04B1/12

CPC classification number: H04B1/123 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/0292

Abstract: There is described a receiver (4) of a signal communication apparatus; the apparatus comprising a transmitter (1) for transmitting the signals, the receiver (4) for receiving the signals and a galvanically isolated wireless interface (3) interposed between the transmitter and the receiver and comprising a transmitting antenna (L1) and a receiving antenna (L2). The receiver comprises a disturbance rejection circuit (6, 52) coupled to the receiving antenna (L2) and capable of compensating for the parasite currents flowing between the transmitting antenna and the receiving antenna at the potential variations between the input and output of the galvanic isolation interface.

Abstract translation: 描述了信号通信设备的接收机（4）; 该装置包括用于发送信号的发射机（1），用于接收信号的接收机（4）和插在发射机和接收机之间的电隔离无线接口（3），包括发射天线（L1）和接收天线 （L2）。 接收机包括耦合到接收天线（L2）的干扰抑制电路（6,52），并且能够以电隔离的输入和输出之间的电势变化补偿在发射天线和接收天线之间流动的寄生电流 接口。

公开(公告)号：EP2282405A2

公开(公告)日：2011-02-09

申请号：EP10169812.4

申请日：2010-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Lombardo, Giovanni ,  Giombanco, Salvatore ,  Grande, Michele ,  Tumminaro, Salvatore ,  Marino, Filippo

IPC: H04B1/10

CPC classification number: H04B1/10

Abstract: There is described a receiver (4) of a signal communication apparatus; the apparatus comprises a transmitter (1) adapted to transmit coded signals, the receiver (4) for receiving the signal and a wireless interface (3) interposed between the transmitter and the receiver and comprising a transmitting antenna (L1) and a receiving antenna (L2). The receiver comprises decoding means (12) of the received signal and first means (9, 10) coupled to the receiving antenna (L2) and capable of triggering said decoding means of the received signal if the value of the received signal is outside a logical hysteresis consisting of a first logic threshold (TH_LO) having a value smaller than the value of the direct current component of the received signal and a second logic threshold (TH_HI) having a value greater than the value of the direct current component (Irde) of the received signal.

Abstract translation: 描述了信号通信设备的接收机（4）; 该装置包括适于发送编码信号的发射机（1），用于接收信号的接收机（4）和插在发射机与接收机之间的无线接口（3），包括发射天线（L1）和接收天线 L2）。 接收机包括接收信号的解码装置（12）和耦合到接收天线（L2）的第一装置（9,10），并且如果接收信号的值在逻辑 具有小于接收信号的直流分量的值的第一逻辑阈值（TH_LO）和具有大于直流分量（Irde）的值的第二逻辑阈值（TH_HI）的第二逻辑阈值 接收信号。

公开(公告)号：EP2280488A1

公开(公告)日：2011-02-02

申请号：EP10167420.8

申请日：2010-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Giombanco, Salvatore ,  Lombardo, Giovanni ,  Tumminaro, Salvatore ,  Marino, Filippo

IPC: H04B1/16 ,  H04L7/033 ,  G06F13/38

CPC classification number: H04B1/16 ,  H04L7/0008 ,  H04L25/0264 ,  H04L25/0268 ,  H04L27/02

Abstract: A transmission and reception apparatus for at least one digital data signal (DATA) is described. The digital data signal is characterized by two logical levels, first and second logical levels, with said second logical level higher than the first logical level. The apparatus comprises a transmitter (6, 1), a receiver (3, 7) and a galvanically isolated wireless interface (5) arranged between the transmitter and the receiver and comprising a transmitting antenna and a receiving antenna formed by a pair of coils; said transmitter, receiver and wireless interface are arranged so as to form a two-level isolated digital channel and the transmitter comprises means (6, 1) adapted to send a synchronization signal (CLOCK) to the receiver. The receiver comprises means (7, 71, 72) adapted to synchronize the receiver and the transmitter by means of the received synchronization signal (CLOCK) and the transmitter comprises further means (62, 61) adapted to send said digital data signal (DATA) upon the synchronization of the receiver and transmitter; the means (7, 71, 72) of the receiver comprising at least one memory element (71) configured to memorize, during the reception of said digital data signal (DATA), the information relative to the received synchronization signal (CLOCK). ( Fig. 6 )

Abstract translation: 描述用于至少一个数字数据信号（DATA）的发送和接收装置。 数字数据信号的特征在于具有高于第一逻辑电平的所述第二逻辑电平的两个逻辑电平的第一和第二逻辑电平。 该装置包括发射机（6,1），接收机（3,7）和布置在发射机和接收机之间的电隔离无线接口（5），并且包括由一对线圈形成的发射天线和接收天线; 所述发射机，接收机和无线接口被布置成形成两级隔离数字信道，并且发射机包括适于向接收机发送同步信号（CLOCK）的装置（6,1）。 接收机包括适于通过所接收的同步信号（CLOCK）使接收机和发射机同步的装置（7,71,72），并且发射机包括适于发送所述数字数据信号（DATA）的另外的装置（62,61） 在接收机和发射机同步时; 所述接收机的装置（7,71,72）包括至少一个存储器元件（71），所述至少一个存储器元件被配置为在所述数字数据信号（DATA）的接收期间存储关于所接收的同步信号（CLOCK）的信息。 （图6）

公开(公告)号：EP1793484B1

公开(公告)日：2010-02-24

申请号：EP05425865.2

申请日：2005-12-02

Applicant: STMicroelectronics S.r.l.

Inventor： Cannella, Eliana ,  Adragna, Claudio ,  Marino, Filippo ,  Tumminaro, Salvatore

IPC: H02M1/38 ,  H02M3/337

CPC classification number: H02M1/38 ,  H02M3/3376

公开(公告)号：EP1793484A1

公开(公告)日：2007-06-06

申请号：EP05425865.2

申请日：2005-12-02

Applicant: STMicroelectronics S.r.l.

Inventor： Cannella, Eliana ,  Adragna, Claudio ,  Marino, Filippo ,  Tumminaro, Salvatore

IPC: H02M1/088 ,  H02M1/00

CPC classification number: H02M1/38 ,  H02M3/3376

Abstract: Described herein is a device for driving a converter circuit that supplies a charge via a first electronic switch (LS) and a second electronic switch (HS) alternately turned on and off, with a first dead-time interval between turning-off of the first electronic switch and turning-on of the second electronic switch (HS) and a second dead-time interval between turning-off of the second electronic switch (HS) and turning-on of the first electronic switch. Turning-off of the second electronic switch (HS) is controlled as a function of a feedback signal (F) coming from the load (L). The device comprises:
- a generator module (11a, C) for generating a memory signal (V c ), indicating the duration of the first dead-time interval; and
- a delay module (11b, C, 14, 18, 20), sensitive to said memory signal (V c ) for controlling turning-on of the first electronic switch with a delay, with respect to turning-off of the second electronic switch (HS), identified by the aforesaid memory signal (V C ), so that the second dead-time interval has a duration substantially equal to the duration of the first dead-time interval.

Abstract translation: 这里描述的是用于驱动经由第一电子开关（LS）和第二电子开关（HS）交替打开和关闭的电荷的转换器电路的装置，其中第一 电子开关和第二电子开关（HS）的接通以及第二电子开关（HS）的断开和第一电子开关的接通之间的第二死区间隔。 作为来自负载（L）的反馈信号（F）的函数控制第二电子开关（HS）的断开。 该装置包括： - 发生器模块（11a，C），用于产生指示第一死区时间间隔的持续时间的存储信号（V c）; 以及 - 延迟模块（11b，C，14,18,20），对于所述存储器信号（V c）敏感，用于相对于所述第二电子装置的关断而延迟地控制所述第一电子开关的接通 开关（HS），由上述存储信号（VC）识别，使得第二死区间隔的持续时间基本上等于第一死区间隔的持续时间。

公开(公告)号：EP1094606A1

公开(公告)日：2001-04-25

申请号：EP99830666.6

申请日：1999-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Capici, Salvatore Vincenzo ,  Marino, Filippo

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03K17/04123

Abstract: The invention relates to a driver circuit for P-channel MOS switches, of the type comprising: a power transistor (2) having a control terminal (G) and having first (D) and second (S) conduction terminals; a controlled current generator (ION) connected to said control terminal (G) for turning on the power transistor (2); a control circuit (5) for controlling the turning on of said current generator (ION); and a protection circuit (3) coupled to said control terminal (G). The driver circuit (1) further comprises a second current generator (IOFF) connected to the control terminal (G) of the power transistor (2) and in turn driven by the control circuit (5) to control the transistor turn-off. Advantageously, the control circuit (5) also receives a control signal (STOP) from the protection circuit (3) at the end of the latter's action.

Abstract translation: 本发明涉及一种用于P沟道MOS开关的驱动电路，其特征在于包括：功率晶体管（2），具有控制端（G）并具有第一（D）和第二（S）导通端; 连接到所述控制端子（G）的用于导通功率晶体管（2）的受控电流发生器（ION）; 用于控制所述电流发生器（ION）的导通的控制电路（5）; 以及耦合到所述控制端子（G）的保护电路（3）。 驱动器电路（1）还包括连接到功率晶体管（2）的控制端（G）的第二电流发生器（IOFF），并由控制电路（5）驱动以控制晶体管截止。 有利地，控制电路（5）还在后者动作结束时从保护电路（3）接收控制信号（STOP）。

公开(公告)号：EP0943975A1

公开(公告)日：1999-09-22

申请号：EP98830144.6

申请日：1998-03-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marino, Filippo

IPC: G05F3/20

CPC classification number: G05F3/205 ,  G05F1/618

Abstract: A control circuit comprising a plurality of input terminals (HSTRAP,HSRC) and at least one output terminal (POLEPI) for biasing a floating well (EPI) in a semiconductor integrated circuit structure, and comprising a first transistor (NCH1) which has its conduction terminals connected between a first input terminal (HSTRAP) and an output terminal (POLEPI), and a second transistor (PCH1) which has its conduction terminals connected between a second input terminal (HSTRAP) and the output terminal (POLEPI), wherein the output terminal (POLEPI) is coupled to each of the control terminals of said first and second transistors through a regulator (Dz).

Abstract translation: 一种控制电路，包括多个输入端子（HSTRAP，HSRC）和至少一个用于偏置半导体集成电路结构中的浮动阱（EPI）的输出端子（POLEPI），并且包括具有导通的第一晶体管（NCH1） 连接在第一输入端子（HSTRAP）和输出端子（POLEPI）之间的端子以及其导通端子连接在第二输入端子（HSTRAP）和输出端子（POLEPI）之间）的第二晶体管（PCH1） 端子（POLEPI）通过调节器（Dz）耦合到所述第一和第二晶体管的每个控制端子。

公开(公告)号：EP1990916B1

公开(公告)日：2012-04-11

申请号：EP08155068.3

申请日：2008-04-24

Applicant: STMicroelectronics S.r.l.

Inventor： Rapisarda, Andrea ,  Marino, Filippo ,  D'Arrigo, Angelo Maria

IPC: H03K4/502 ,  H03K7/06 ,  H03B23/00

CPC classification number: H03K7/06 ,  H03B23/00 ,  H04B15/02 ,  H04B2215/067