公开(公告)号：EP1566888A1

公开(公告)日：2005-08-24

申请号：EP04425100.7

申请日：2004-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Nagari, Angelo

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00071

Abstract: The circuit comprises a first ring oscillator (OSC1) comprising an odd number of inverting elements, a delay element (DA) and an output terminal (N); the delay element (DA) responds to a pulse at its input (IN-DA) with a predetermined time delay (d(DA)) with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator (OSC2) equal to the first, having an output terminal connected to the output terminal (N) of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output (N) of the first and the second oscillator. At least one of the inverting elements of the first oscillator (OSC1) and at least one of the inverting elements of the second oscillator (OSC2) form part of the bistable logic circuit.

Abstract translation: 该电路包括包括奇数个反相元件的第一环形振荡器（OSC1），延迟元件（DA）和输出端子（N）; 延迟元件（DA）相对于输入脉冲的预定边缘以预定的时间延迟（d（DA））在其输入端（IN-DA）处响应脉冲，并且相对于另一边缘基本上没有时间延迟 的输入脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括等于第一环路振荡器（OSC2）的第二环形振荡器（OSC2），其具有连接到输出端子（N）的输出端子 第一振荡器和双稳态逻辑电路，其输出端连接到第一和第二振荡器的公共输出端（N）。 第一振荡器（OSC1）的反相元件和第二振荡器（OSC2）的反相元件中的至少一个的至少一个形成双稳态逻辑电路的一部分。

公开(公告)号：EP1217744B1

公开(公告)日：2004-03-24

申请号：EP00830836.3

申请日：2000-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nagari, Angelo ,  Nicollini, Germano

IPC: H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/00 ,  H03K19/017 ,  G11C7/10

CPC classification number: G11C7/1051 ,  H03K19/00361

公开(公告)号：EP1372265A1

公开(公告)日：2003-12-17

申请号：EP02425378.3

申请日：2002-06-10

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nagari, Angelo ,  Nicollini, Germano

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K17/166 ,  H03K17/164

Abstract: A digital system comprises a digital data processing unit (PROC), at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit (13) connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means (14, 15, IGEN1, IGEN2) for fixing the switching current to a value that is substantially constant and independent of the load and means (SN2-4, SP2-4) for selectively setting the value of the switching current and the processing unit (PROC) comprises means (REG) for storing a predetermined parameter; said means (REG) are connected to the selective setting means (SN2-4, SP2-4) for setting the values of the switching current as functions of the predetermined parameter.

Abstract translation: 一种数字系统，包括一个数字数据处理单元（PROC），连接到所述处理单元响应于来自所述处理单元和至少一个用户单元（13）到达的数字信号，以产生输出信号的至少一个输出缓冲器连接作为输出缓冲 负载。 与以确保没有输出缓冲区的切换电流的图可以被设置为不同的值，输出缓冲器包括装置（14，15，IGEN1，IGEN2），用于切换电流固定为一个值那样基本上是恒定的和独立的 负载和用于有选择地设定切换电流和所述处理单元（PROC）的值的装置（SN2-4，SP2-4）包括用于存储预定参数的装置（REG）; 所述装置（REG）被连接到所述选择性设定装置（SN2-4，SP2-4）用于设定切换电流的值作为预定参数的功能。

公开(公告)号：EP0903862B1

公开(公告)日：2003-06-25

申请号：EP97830458.2

申请日：1997-09-19

Applicant: STMicroelectronics S.r.l.

Inventor： Nagari, Angelo ,  Nicollini, Germano

IPC: H03M3/00 ,  H03H19/00

CPC classification number: H03H19/004 ,  H03M3/342 ,  H03M3/502

公开(公告)号：EP0678980B1

公开(公告)日：1999-08-04

申请号：EP94830189.0

申请日：1994-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Nicollini, Germano ,  Nagari, Angelo

IPC: H03H19/00

CPC classification number: G11C27/024 ,  G11C27/026 ,  H03F3/005 ,  H03H19/004 ,  H03K5/249

公开(公告)号：EP0903862A1

公开(公告)日：1999-03-24

申请号：EP97830458.2

申请日：1997-09-19

Applicant: STMicroelectronics S.r.l.

Inventor： Nagari, Angelo ,  Nicollini, Germano

IPC: H03M3/00 ,  H03H19/00

CPC classification number: H03H19/004 ,  H03M3/342 ,  H03M3/502

Abstract: A ΣΔ digital/analog converter has a signal reconstructing multirate low pass filter realized as a switched capacitor fully differential, double sample structure wherein the input stage of the filter employs only two sampling capacitors, switched alternately on the two inputs of the stage and further includes two delay circuits (z -1 ) in the feed line of the bitstream towards one of the two inputs of the multistage SC filter. The zeroes so introduced in the transfer function reduce the noise energy in the vicinity of frequencies f s /2 n , preserving the SNR even with a relatively large mismatch between the capacitors.

Abstract translation: Σ-Δ数/模转换器具有重构实现为开关电容器全差分，双样本结构worin滤波器的输入级仅采用两个采样电容器的多速率的低通滤波器的信号，交替地切换在舞台上和另外的两个输入端 包括在比特流中的朝向的多级SC滤波器的两个输入之一的进料管线两个延迟电路（Z <-1>）。 在传递函数中，以便介绍了零减少在频率fs / 2的的附近的噪声能量，保留SNR甚至与电容器之间的相对大的失配。

公开(公告)号：EP0901233A1

公开(公告)日：1999-03-10

申请号：EP97830440.0

申请日：1997-09-05

Applicant: STMicroelectronics S.r.l.

Inventor： Nagari, Angelo ,  Nicollini, Germano

IPC: H03M3/00 ,  H03M3/02

CPC classification number: H03M3/342 ,  H03M3/43 ,  H03M3/438

Abstract: A second-order double-sampled analog/digital ΣΔ converter uses two fully differential switched-capacitors integrators coupled in cascade; the first integrator has a fully-floating double-sampled, bilinear switched capacitor input structure, whereas the second integrator has a double-sampled linear switched-capacitor input structure, achieving an excellent SNR with a reduced number of switches for a low consumption.

Abstract translation: 二阶双采样模拟/数字SIGMA DELTA转换器使用两个串联耦合的全差分开关电容积分器; 第一个积分器具有全浮动双采样双线性开关电容器输入结构，而第二个积分器具有双采样线性开关电容输入结构，实现了低功耗数量少的开关的极好的SNR。