公开(公告)号：EP2302791A1

公开(公告)日：2011-03-30

申请号：EP10181300.4

申请日：2010-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri Pierangelo ,  Guanziroli, Federico ,  Nicollini, Germano

IPC: H03H1/02 ,  H03H7/12 ,  H03H11/12

CPC classification number: H03H5/12

Abstract: The present invention relates to an electronic regulation device (100) of a variable capacitance of an integrated circuit having a time parameter depending on said variable capacitance. The regulation device comprises a regulation loop (105), and is configured to generate in output a plurality of binary regulation signals (B0, B1, B2, B3).
Such regulation device comprises a block (102) of switching capacitors that comprises a first array (112; 116) of capacitors that can be activated/deactivated based on the binary regulation signals (B0, B1, B2, B3) to be selectively connected in parallel therebetween. Such first array includes capacitors having respective binarily increasing capacitances starting from a first minimum capacitive value (1CB; 1CD). The block (102) is characterized in that it further comprises at least one second array (111; 113, 114, 115) of switching capacitors that can be activated/deactivated based on the binary regulation signals (B0, B1, B2, B3) to be selectively connected in parallel between them and to said first array capacitors. The second array at least partially includes capacitors (Ca2, Ca3, Ca4; Ca2', Ca3') having binarily increasing capacitances starting from a second minimum capacitive value (1CA) that is different from said first minimum capacitive value (1CB).

Abstract translation: 本发明涉及在具有时间参数取决于所述可变电容的集成电路的一个可变电容的电子调节装置（100）。 调节装置包括一个调节环（105），并且被配置在输出，以产生调节二进制信号（B0，B1，B2，B3）的复数。 搜索调节装置包括开关电容器块（102）做了包括第一阵列（112; 116）的电容器也可以被激活/基于选择性地连接在二进制调节信号（B0，B1，B2，B3）去激活 并行之间那里。 搜索第一阵列包括具有电容respectivement binarily增加从第一最小电容值（1CB; 1CD）开始电容器。 块（102）的特征在于，这样做是还包括至少一个第二阵列（111; 113，114，115）的切换电容器也可以被激活/基于二进制调节信号去激活（B0，B1，B2，B3） 选择性地被连接在它们之间，并与所述电容器firstArray平行。 第二阵列至少部分地包括电容器（CA2，CA3，CA4;钙”，CA 3' ），其具有增加binarily从第二最小电容值（1CA）开始电容确实是从所述第一电容最小值（1CB）不同。

公开(公告)号：EP1710917A1

公开(公告)日：2006-10-11

申请号：EP06116241.8

申请日：2003-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nicollini, Germano ,  Martignone, Riccardo

IPC: H03M1/68

CPC classification number: H03M1/687 ,  H03M1/68 ,  H03M1/745 ,  H03M1/765

Abstract: A digital to analog converter to convert into an analog quantity a digital code of L bits, comprising
- a first group of L current generators codified in binary form (MDON-MD2N),
- first selection means (SDON-SD2N) of the L current generators,
- means for conveying onto a common output node (N3) the current (IL) of the selected generators,
- control means (TRANSCOD-3BIT') to selectively operate the selection means (SD0N-SD2N) according to the digital code of L bits.
The converter further comprises a second group of L current generators (MD0P-MD2P) codified in binary form and second selection means (SD0P-SD2P) of the second group of L current generators.
The control means comprise a selection logic that alternatively habilitates the use of the first or the second group of generators according to whether the digital code to be converted does (D11=1) or does not (D11=0) exceed, respectively, a predetermined value.

Abstract translation: 一种数模转换器，用于将L位的数字码转换为模拟量，包括：以二进制形式编码的第一组L电流发生器（MDON-MD2N），L电流的第一选择装置（SDON-SD2N） 发电机， - 用于将所选发电机的电流（IL）传送到公共输出节点（N3）的装置， - 控制装置（TRANSCOD-3BIT'），以根据数字代码选择性地操作选择装置（SD0N-SD2N） L位。 转换器还包括以二进制形式编码的第二组L电流发生器（MD0P-MD2P）和第二组L电流发生器的第二选择装置（SD0P-SD2P）。 所述控制装置包括选择逻辑，所述选择逻辑根据所述要转换的数字码是否（D11 = 1）或不（D11 = 0）分别超过预定的 值。

公开(公告)号：EP1601113A1

公开(公告)日：2005-11-30

申请号：EP04425375.5

申请日：2004-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Nicollini, Germano ,  Confalonieri, Pierangelo ,  Martignone, Riccardo

IPC: H04B1/707

CPC classification number: H04B1/707

Abstract: There is described a wide-band transmission system, particularly for employment in cellular telephony systems that adopt the WCDMA standard. The system comprises means for generating two digital signals containing information to be transmitted, means for converting into analog form the two signals comprising, for each signal to be converted, a digital-analog converter (DAC) followed by a low-pass filter (LOW-PASS), means for modulating both in phase and in quadrature a radio frequency carrier with the two signals issuing from the low-pass filters (LOW-PASS), and means for transmitting the modulated carrier in accordance with a predetermined emission mask. If the system is to be capable of being integrated into an area of small extent and is to have a low current consumption, the low-pass filter (LOW-PASS) is an active filter of the second order continuous in time and current-coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at a sampling frequency greater than the Nyquist frequency by at least as much as is necessary to respect the predetermined emission mask.

Abstract translation: 描述了一种宽带传输系统，特别是在采用WCDMA标准的蜂窝电话系统中的就业。 该系统包括用于产生包含要发送的信息的两个数字信号的装置，用于将两个信号转换成模拟形式的装置，对于每个要转换的信号，包括数模转换器（DAC）和随后的低通滤波器（LOW -PASS），用于利用从低通滤波器（LOW-PASS）发出的两个信号同时和正交调制无线电频率载波的装置，以及用于根据预定的发射掩模传送调制载波的装置。 如果系统能够集成到小范围的区域并且具有低电流消耗，则低通滤波器（LOW-PASS）是时间上连续的二阶有源滤波器和电流耦合 数字模拟转换器（DAC）的输出端和数模转换器（DAC）是以大于奈奎斯特频率的采样频率工作的电流导向型转换器，其至少必须相当于必须的 预定的发射掩模。

公开(公告)号：EP1494357A1

公开(公告)日：2005-01-05

申请号：EP03425439.1

申请日：2003-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： Nicollini, Germano ,  Pinna, Carlo

IPC: H03M1/12 ,  G11C27/02

CPC classification number: G11C27/024 ,  H03M1/1245

Abstract: A boosted sampling circuit easy to realize, the input voltage of which may be greater than the maximum voltage level allowed by prior art circuits or even equal to the supply voltage, is disclosed.
This result is attained by connecting the control nodes of the switches M2, M3 and M4 to the input node while the first control phase F1D is active, and by connecting a current terminal of the transistor M2 to a certain voltage for protecting it from breakdowns.
A relative method of driving a boosted sampling circuit is also disclosed.

公开(公告)号：EP1217744A1

公开(公告)日：2002-06-26

申请号：EP00830836.3

申请日：2000-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nagari, Angelo ,  Nicollini, Germano

IPC: H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/00 ,  H03K19/017 ,  G11C7/10

CPC classification number: G11C7/1051 ,  H03K19/00361

Abstract: The buffer has an output stage (10) formed by two complementary MOS transistors (MPOUT, MNOUT) connected so as to operate in phase opposition between the supply terminals (VDD, earth) and two driver stages (14 and 15) having the input (IN) in common. Each driver stage (14, 15) has a first branch comprising a current-generator (MN4, MP4) connected between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a supply terminal (earth, VDD) and an electronic switch (MP1, MN1) controlled by the input (IN) and connected between the same gate electrode and the other supply terminal (VDD, earth), and a second branch which comprises, connected in series, a transistor connected as a diode (MP3, MN3) and an electronic switch (MP2, MN2) controlled by the output (OUT), and is arranged between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a respective supply terminal (VDD, earth). The buffer can control a load (13) with a constant switching current, is simple in structure, and occupies a small area.

Abstract translation: 缓冲器具有由两个互补MOS晶体管（MPOUT，MNOUT）形成的输出级（10），以在电源端子（VDD，接地）和具有输入端的两个驱动器级（14和15）之间相对操作， IN）的共同点。 每个驱动器级（14,15）具有第一分支，包括连接在待驱动晶体管（MPOUT，MNOUT）的栅电极和电源端（地，VDD）之间的电流发生器（MN4，MP4）和电子 开关（MP1，MN1）由输入（IN）控制并连接在同一个栅极和另一个电源端子（VDD，接地）之间，第二个分支包括串联连接为二极管的晶体管（MP3 ，MN3）和由输出（OUT）控制的电子开关（MP2，MN2），并且被布置在待驱动晶体管（MPOUT，MNOUT）的栅电极和相应的电源端子（VDD，接地）之间。 缓冲器可以用恒定的开关电流控制负载（13），结构简单，占用面积小。

公开(公告)号：EP0375017B1

公开(公告)日：2005-06-01

申请号：EP89203109.7

申请日：1989-12-07

Applicant: STMicroelectronics S.r.l.

Inventor： Nicollini, Germano

IPC: H03H19/00

CPC classification number: H03F3/005 ,  H03H19/004

公开(公告)号：EP0901233B1

公开(公告)日：2005-03-02

申请号：EP97830440.0

申请日：1997-09-05

Applicant: STMicroelectronics S.r.l.

Inventor： Nagari, Angelo ,  Nicollini, Germano

IPC: H03M3/00 ,  H03M3/02

CPC classification number: H03M3/342 ,  H03M3/43 ,  H03M3/438

公开(公告)号：EP1458102A1

公开(公告)日：2004-09-15

申请号：EP03425160.3

申请日：2003-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nicollini, Germano ,  Martignone, Ricardo

IPC: H03M1/68

CPC classification number: H03M1/687 ,  H03M1/68 ,  H03M1/745 ,  H03M1/765

Abstract: The described digital-analog converter comprises a first section (MSB) for converting the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (ΔV1), a second section (LSB) to convert the less significant bits of the digital code into a current, means for transforming the current (IL) of the second section (LSB) into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (ΔV2) equal to 1/2 L of the product of the first voltage step (ΔV1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted, control means (DEC-9BIT; TRANSCOD-3BIT) of the first and the second section and summation means (OPA2) for obtaining an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summation means have resistive feedback means comprising a voltage divider (R3, R4) and the means for transforming the current (IL) into a second voltage comprise a conversion resistor (R4) that forms part of the voltage divider.

Abstract translation: 所描述的数模转换器包括用于将数字代码的更高有效位转换为多个分立电压的第一电压（Vin）的第一部分（MSB），该多个离散电压是预定的第一电压步长（DELTA V1）的整数倍， ，用于将数字代码的较低有效位转换为电流的第二部分（LSB），用于将第二部分（LSB）的电流（IL）变换为多个整数倍的多个离散电压的第二电压的装置 第二电压步长（DELTA V2）等于第一电压步长（DELTA V1）乘以预定系数的乘积的1/2

公开(公告)号：EP1071206B1

公开(公告)日：2004-06-02

申请号：EP99830462.0

申请日：1999-07-20

Applicant: STMicroelectronics S.r.l.

Inventor： Pernici, Sergio ,  Nicollini, Germano

IPC: H03G3/34

CPC classification number: H03G3/348

公开(公告)号：EP1052831A1

公开(公告)日：2000-11-15

申请号：EP99830296.2

申请日：1999-05-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nicollini, Germano ,  Pernici, Sergio

IPC: H04M1/60 ,  H03G3/34

CPC classification number: H03F1/305 ,  H03G3/348 ,  H04M1/6016

Abstract: The receiving section comprises a final stage (12), an electroacoustic transducer (13) having a first terminal connected to the ground of the circuit, a unit for controlling switching on/off, a source (30) of a reference voltage, a switch (21) which can adopt a first position or a second position in order to connect the second terminal of the transducer (13) selectively, via a capacitor (Cest), to the reference-voltage terminal (REF) or to an output terminal (OUT) of the final stage (12), respectively, and control means (20) which respond to signals (PD) of the unit for controlling switching on/off in order to activate or to deactivate the final stage (12) and the reference-voltage source (30) and to operate the switch (21) in accordance with a predetermined time program.
The receiving section operates with the same immunity to disturbances as a fully balanced structure, even though the transducer (13) is not connected between two balanced outputs.

Abstract translation: 接收部分包括最终级（12），具有连接到电路接地的第一端子的电声换能器（13），用于控制接通/断开的单元，参考电压的源（30），开关 （21），其可以采用第一位置或第二位置，以便经由电容器（Cest）选择性地将所述换能器（13）的第二端子连接到所述基准电压端子（REF）或输出端子 OUT）和控制装置（20），其响应于用于控制开关的单元的信号（PD），以便激活或停用最终级（12）和参考 电压源（30），并根据预定的时间程序操作开关（21）。 即使传感器（13）没有连接在两个平衡输出之间，接收部分也具有与完全平衡的结构相同的扰动抗扰度。