公开(公告)号：EP1143454A1

公开(公告)日：2001-10-10

申请号：EP00830239.0

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C16/12

CPC classification number: G11C16/12

Abstract: The integrated device (100) comprises a PMOS transistor (101) and a voltage selector (1) having an output (6g) connected to the bulk terminal (101d) of the PMOS transistor (101). The voltage selector (1) comprises an input stage (2) supplying (2c) a supply voltage (Vdd) or a programming voltage (Vpp) according to whether the device (100) is in a reading step or in a programming step; a comparator (3) connected to the output (2c) of the input stage (2), receiving a boosted voltage (Vboost), and generating (3g) a first control signal (OC), the state whereof depends upon the comparison of the voltages at the inputs of the comparator (3); a logic circuit (4) connected to the output (3g) of the comparator (3) and generating a second control signal (VDDIS), the state whereof depends upon the state of the first control signal (OC) and of a third-level signal (VTL); and a switching circuit (6) controlled by the first control signal (OC), by the second control signal (VDDIS), and by the third-level signal (VTL) and supplying (6g) each time the highest among the supply voltage (Vdd), the boosted voltage (Vboost), and the programming voltage (Vpp).

Abstract translation: 集成器件（100）包括PMOS晶体管（101）和电压选择器（1），其具有连接到PMOS晶体管（101）的体积端子（101d）的输出（6g）。 电压选择器（1）包括根据装置（100）是处于读取步骤还是编程步骤中的（2c）供应电压（Vdd）或编程电压（Vpp）的输入级（2） 连接到输入级（2）的输出（2c）的比较器（3），接收升压电压（Vboost），并产生（3g）第一控制信号（OC），其状态取决于 比较器（3）输入端的电压; 连接到比较器（3）的输出（3g）并产生第二控制信号（VDDIS）的逻辑电路（4），其状态取决于第一控制信号（OC）的状态和第三级 信号（VTL）; 以及由第一控制信号（OC），第二控制信号（VDDIS）和第三电平信号（VTL）控制的开关电路（6），并且每次在电源电压（ Vdd），升压电压（Vboost）和编程电压（Vpp）。

公开(公告)号：EP1143451A1

公开(公告)日：2001-10-10

申请号：EP00830238.2

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: The charge pump (1) comprises a phase-generator circuit (6) generating phase signals (A, B) and comprising an oscillator circuit (12.1-12.3) supplying a clock signal (CK), a current-limitation circuit (24.1-24.3) to limit the current flowing in the oscillator circuit, and a control circuit (26') supplying on an output (32a) a control signal (V REF ) supplied to the current-limitation circuit. The control circuit (26') comprises a first current mirror (60) connected to a ground line (22), a second current mirror (62) connected to a supply line (20), a cascode structure (64), arranged between the first and the second current mirrors (60, 62) and connected to the output (32a) of the control circuit (26') to compensate the effects on the control signal (V REF ) caused by sharp relative variations between the potential (V DD ) of the supply line and the potential (V GND ) of the ground line, and a compensation circuit (70) to compensate the effects on the control signal (V REF ) caused by sharp relative variations between the potential (V DD ) of the supply line and the potential (V GND ) of the ground line and by slow variations in temperature.

Abstract translation: 电荷泵（1）包括产生相位信号（A，B）的相位发生器电路（6），并且包括提供时钟信号（CK）的振荡器电路（12.1-12.3），电流限制电路（24.1-24.3 ）以限制在振荡器电路中流动的电流，以及向输出（32a）提供提供给电流限制电路的控制信号（VREF）的控制电路（26'）。 控制电路（26'）包括连接到地线（22）的第一电流镜（60），连接到电源线（20）的第二电流镜（62），共源共栅结构（64） 第一和第二电流镜（60,62），并且连接到控制电路（26'）的输出端（32a），以补偿由控制信号（VREF）的电位（VDD）之间的尖锐相对变化引起的对控制信号 地线的电源线和电位（VGND）以及补偿电路（70），用于补偿由供电线的电位（VDD）与电位之间的尖锐相对变化引起的对控制信号（VREF）的影响 （VGND）和温度变化缓慢。