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    Voltage boosting device
    1.
    发明公开
    Voltage boosting device 有权
    Spannungserhöhungsvorrichtung

    公开(公告)号：EP1124313A1

    公开(公告)日：2001-08-16

    申请号：EP00830088.1

    申请日：2000-02-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

    IPC: H02M3/07

    CPC classification number: H02M3/07

    Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator (11) and a charge pump (13) and having an output terminal (10); the voltage regulator (11) having a regulation terminal connected to the output terminal (10), and an output (16) supplying a control voltage (V L ); the read charge pump (13) having an output connected to the output terminal (10) and supplying a read voltage (V R ). The device further includes an enable circuit (12) connected to the output (16) and having a pump enable output (17) connected to a charge pump enable terminal (13) and supplying a pump enable signal (PE). The pump enable signal (PE) is set at a first logic level so as to activate the charge pump (13) when the read voltage (V R ) is lower than a nominal value. In addition, the device generates a power-up sync signal (ATDS) which activates a read operation when the read voltage (V R ) reaches its nominal value and a chip enable signal (CE) is set at an active value.

    Abstract translation: 一种用于加速包括电压调节器（11）和电荷泵（13）并具有输出端子（10）的多电平非易失性存储器的上电的升压装置; 具有连接到输出端子（10）的调节端子的调压器（11）和提供控制电压（VL）的输出端（16）; 所述读取电荷泵（13）具有连接到所述输出端子（10）并提供读取电压（VR）的输出。 该装置还包括连接到输出端（16）并且具有连接到电荷泵使能端子（13）并提供泵使能信号（PE）的泵使能输出（17）的使能电路（12）。 泵使能信号（PE）被设置在第一逻辑电平，以便当读取电压（VR）低于额定值时激活电荷泵（13）。 此外，器件产生上电同步信号（ATDS），当上述读取电压（VR）达到其标称值且芯片使能信号（CE）被设置为有效值时，该同步信号激活读取操作。

    Multiemitter bipolar transistor for bandgap reference circuits
    3.
    发明公开
    Multiemitter bipolar transistor for bandgap reference circuits 审中-公开
    Vielfachemitter-BipolartransistorfürBandabstands-Referenzschaltungen

    公开(公告)号：EP1220321A1

    公开(公告)日：2002-07-03

    申请号：EP00830851.2

    申请日：2000-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vendrame, Loris ,  Caprara, Paolo ,  Oddone, Giorgio ,  Barcella, Antonio

    IPC: H01L29/732 ,  H01L29/08

    CPC classification number: H01L29/7322 ,  H01L29/0813

    Abstract: The present invention relates a transistor comprising a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of said first type (P+) of conductivity inside said substrate region (14) and adjacent to a first terminal (C) of said transistor, a well (11) of second type (N) of conductivity placed inside said substrate region (14), characterized in that said well (11) of second type (N) of conductivity comprises at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of said transistor, and a plurality of third contact regions (10) of said first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, ..., E3) of said transistor interposed each one (10) other (12) by proper insulating shapes (20).

    Abstract translation: 本发明涉及一种晶体管，其包括在具有相同类型（P）导电性的半导体材料层中的第一类型（P）的基底区域（14），至少第一类型的第一接触区域（13） （14）内并与所述晶体管的第一端（C）相邻的电导率（P +），放置在所述衬底区域（14）内的第二类型（N）导电性阱（11），其特征在于： 所述第二类型（N）的导体的阱（11）包括与所述晶体管的第二端子（B）的区域相邻的至少第二接触区域（N）的第二接触区域（12），并且多个 与所述晶体管的第三端子（E1，...，E3）的多个区域相邻的所述第一类型导电性（P +）的第三接触区域（10）通过适当地插入每个（10）另一个（12） 绝缘形状（20）。

    Reference cells matrix structure for reading data in a nonvolatile memory device
    7.
    发明公开
    Reference cells matrix structure for reading data in a nonvolatile memory device 有权
    Referenzzellenmatrixanordnung zum Datenlesen在einernichtflüchtigenSpeicheranordnung

    公开(公告)号：EP1160795A1

    公开(公告)日：2001-12-05

    申请号：EP00830393.5

    申请日：2000-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

    IPC: G11C16/28 ,  G11C11/56

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

    Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3).
    Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

    Abstract translation: 本发明涉及一种用于读取包含在电可编程/可擦除的集成非易失性存储器件中的数据的电路结构（1），其包括存储器单元（3）的矩阵（2）和用于比较的至少一个参考单元（4） 在读取阶段期间具有存储器单元（3）。 参考单元（4）被并入参考单元子矩阵（5）中，其在结构上独立于存储单元（3）的矩阵（2）。 还提供了矩阵（2）和子矩阵（5）之间的传导路径，该路径包括连续延伸到矩阵（2）中的参考单元（4）的子矩阵（5）的位线（b1ref） 存储单元（3）

    Circuit structure for programming data in reference cells of a multibit non-volatile memory device
    10.
    发明公开
    Circuit structure for programming data in reference cells of a multibit non-volatile memory device 有权
    参考文献

    公开(公告)号：EP1160794A1

    公开(公告)日：2001-12-05

    申请号：EP00830392.7

    申请日：2000-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

    IPC: G11C11/56 ,  G11C16/28

    CPC classification number: G11C7/1072 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

    Abstract: The invention relates to a circuit structure (1) for programming data in reference cells (3) of an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix of multi-level memory cells and at least one corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell (3) is incorporated, along with other cells of the same type, to a reference cell sub-matrix (4) which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode.
    The bit lines of the sub-matrix (4) branch off to a series of switches (9) which are individually operated by respective control signals REF(i) issued from a logic circuit (8) with the purpose of selectively connecting the bit lines to a single external I/O terminal (10) through a single addressing line (11) of the access DMA mode.

    Abstract translation: 本发明涉及一种用于对电可编程/可擦除集成非易失性存储器件的参考单元（3）中的数据进行编程的电路结构（1），包括多级存储器单元的矩阵和至少一个对应的参考单元 在读取阶段期间与相应的存储器单元进行比较。 参考单元（3）与相同类型的其他单元一起并入参考单元子矩阵（4），该参考单元子矩阵在结构上独立于存储单元矩阵并且在DMA模式下从外部直接访问。 子矩阵（4）的位线分支到由逻辑电路（8）发出的相应控制信号REF（i）分别操作的一系列开关（9），目的是选择性地连接位线 通过访问DMA模式的单个寻址线（11）连接到单个外部I / O端子（10）。

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